diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-17 10:56:26 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-23 15:52:09 +0000 |
| commit | a342f3937e7ce159fd170ab8cd26ba799a3bc9e4 (patch) | |
| tree | 4bd4540ba11286f465272c1fbee62dbf5f9789f8 /src/soc/intel/baytrail | |
| parent | 9856892297ad997f586a1b4dd0a494f3764a0ce2 (diff) | |
| download | coreboot-a342f3937e7ce159fd170ab8cd26ba799a3bc9e4.tar.xz | |
src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/pcie.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/perf_power.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 7208e88d43..3e03ca5d98 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -229,7 +229,7 @@ static void byt_pcie_enable(struct device *dev) static void byt_pciexp_scan_bridge(struct device *dev) { static const struct reg_script wait_for_link_active[] = { - REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000), + REG_PCI_POLL32(LCTL, (1 << 29), (1 << 29), 50000), REG_SCRIPT_END, }; diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 20a066450d..6cddf766c3 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -221,7 +221,7 @@ E(CCU, 0x28, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2 E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en -E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en +E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en |