diff options
| author | Ken Chang <kenc@nvidia.com> | 2014-05-22 10:54:16 +0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-31 05:26:51 +0100 |
| commit | a859aa3df5c56f7d0d2d0969c4de601b93e4c101 (patch) | |
| tree | 93e65df3be79ab72a814fdc6bf79faffaa1312ab /src/soc/intel/baytrail | |
| parent | 9e208bc357b9357c05ad05fe4482ffaeb0047312 (diff) | |
| download | coreboot-a859aa3df5c56f7d0d2d0969c4de601b93e4c101.tar.xz | |
nyan*: Set GEN2 I2C pads to open-drain mode
The VDDIO to GEN2 I2C SCL/SDA pins is 1.8V and the external
pull-up voltage is 3.3V (the external 3.3V > I/O 1.8V) thus
the pinmux E_OD bit of these two pins needs to be set to
ensure GEN2 I2C pads work fine on 3.3V.
BRANCH=nyan
BUG=none
TEST=observed voltage drop from 3.3V to 2.36V on gen2 i2c
on blaze w/o this change. the waveform looks good on both
scl/sda pins w/ this change.
Original-Change-Id: I1b97f0c9c7580d1e532c3bdf7ac8690241ee7ee3
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200996
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2db39166ec525e56a19746f38a867305a2687365)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0c84eade89311baf0a6f180cb5cc9e2145f6b7ea
Reviewed-on: http://review.coreboot.org/7952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail')
0 files changed, 0 insertions, 0 deletions