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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-10 12:44:03 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-16 08:04:09 +0000 |
| commit | 0778c86b3b94490284d0fe686500d29ca791d39d (patch) | |
| tree | ff6a9cb768ff722966d1ecf732ec2e00d60c5a49 /src/soc/intel/baytrail | |
| parent | 040c531158861284b7d21f1e8a26b1f6d4ccad58 (diff) | |
| download | coreboot-0778c86b3b94490284d0fe686500d29ca791d39d.tar.xz | |
sb,soc/intel: Replace smm_southbridge_enable_smi()
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/cpu.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/smm.c | 8 |
2 files changed, 12 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index fbbd84ac1b..59002619df 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -178,6 +178,11 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, smm_state->smbase = staggered_smbase; } +static void post_mp_init(void) +{ + global_smi_enable(); +} + static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, @@ -186,7 +191,7 @@ static const struct mp_ops mp_ops = { .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = relocation_handler, - .post_mp_init = smm_southbridge_enable_smi, + .post_mp_init = post_mp_init, }; void baytrail_init_cpus(struct device *dev) diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 38efe2ba39..58238db627 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -70,9 +70,8 @@ static void smm_southcluster_route_gpios(void) outl(alt_gpio_reg, alt_gpio_smi); } -void smm_southbridge_enable_smi(void) +static void smm_southbridge_enable(uint16_t pm1_events) { - uint16_t pm1_events = PWRBTN_EN | GBL_EN; printk(BIOS_DEBUG, "Enabling SMIs.\n"); if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE]) @@ -94,6 +93,11 @@ void smm_southbridge_enable_smi(void) enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } +void global_smi_enable(void) +{ + smm_southbridge_enable(PWRBTN_EN | GBL_EN); +} + void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* |