diff options
| author | Alexander Couzens <lynxis@fe80.eu> | 2015-11-24 09:46:18 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-28 19:17:05 +0100 |
| commit | 316170e22cd2772e3b01e714ca8d662467b8de0c (patch) | |
| tree | 94fbb740fa342858d6bf9ea69c37367f673bb60b /src/soc/intel/baytrail | |
| parent | edf965a01eab654433a901e15426064b0700c603 (diff) | |
| download | coreboot-316170e22cd2772e3b01e714ca8d662467b8de0c.tar.xz | |
baytrail: fix missing brackets around ir_base to fix IRQ routing
The missing brackets caused other registers, including the IO APIC
enable bit (EAN in OIC) to be overwritten. Bug introduced by
bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer)
Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12525
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/southcluster.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 49c4545e79..090b98802b 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -184,7 +184,7 @@ static void sc_init(device_t dev) { int i; u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); - u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20; + u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20); u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); const struct baytrail_irq_route *ir = &global_baytrail_irq_route; |