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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-05-25 08:52:07 +0300 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-06-15 18:35:52 +0000 |
| commit | 44ef38f70344f44ee53a3883515246172eb75054 (patch) | |
| tree | c6f138d104484327e635c1cac1ccb81dbc15ce42 /src/soc/intel/baytrail | |
| parent | 49c44cdccb936bf1179402b5927a1f477ad4e752 (diff) | |
| download | coreboot-44ef38f70344f44ee53a3883515246172eb75054.tar.xz | |
arch/x86: Remove NO_FIXED_XIP_ROM_SIZE
The variable SETUP_XIP_CACHE provides us a working
alternative.
Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 1fd9c4072c..326dff2467 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT - select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK |