diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-05 10:36:45 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-08 09:46:16 +0000 |
| commit | 88607a4b1002ed6acc7f316f274feea2fd861095 (patch) | |
| tree | e004c85f36109da78872b88875d4f0ea1c30aaff /src/soc/intel/baytrail | |
| parent | d9169f826a3c19a7380a7d73c7126e52eb62e77d (diff) | |
| download | coreboot-88607a4b1002ed6acc7f316f274feea2fd861095.tar.xz | |
src: Use tabs for indentation
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/gpio.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/pmutil.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 5da510486b..451993df2f 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -170,7 +170,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios, } static void setup_gpio_route(const struct soc_gpio_map *sus, - const struct soc_gpio_map *core) + const struct soc_gpio_map *core) { uint32_t route_reg = 0; int i; diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 30e6d1d94b..51c3ea065b 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -52,7 +52,7 @@ uint16_t get_pmbase(void) } static void print_num_status_bits(int num_bits, uint32_t status, - const char *bit_names[]) + const char *bit_names[]) { int i; diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 027e0d8edc..07b801093f 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -97,8 +97,8 @@ static void spi_init(void) } /* Entry from cache-as-ram.inc. */ -void *asmlinkage romstage_main(unsigned long bist, - uint32_t tsc_low, uint32_t tsc_hi) +void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, + uint32_t tsc_hi) { struct romstage_params rp = { .bist = bist, |