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| author | Aaron Durbin <adurbin@chromium.org> | 2016-08-05 21:23:37 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-08 18:37:37 +0200 |
| commit | 16246ea9ce8a5982ec3ad465f1ea12a91abbc39e (patch) | |
| tree | 3d2447ce12aed51589084049e8aba5ed1fd9894d /src/soc/intel/baytrail | |
| parent | 968ddf27e2a238be2aa4757700f279366fde0b2b (diff) | |
| download | coreboot-16246ea9ce8a5982ec3ad465f1ea12a91abbc39e.tar.xz | |
chromeos chipsets: select RTC usage
Since RTC is now a Kconfig ensure RTC is selected on the
x86 chipsets which are in Chrome OS devices. This allows
the eventlog to have proper timestamps instead of all
zeros.
BUG=chrome-os-partner:55993
Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index d58d4dd28e..b79000802e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select REG_SCRIPT + select RTC select SMM_TSEG select SMP select SPI_FLASH |