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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-10-15 12:07:03 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:19:03 +0100 |
| commit | 94b856ef9afaca880909d22b24d5443408c47920 (patch) | |
| tree | 14a76715a13535b5c2991103adf4820f776f1dd5 /src/soc/intel/braswell/Kconfig | |
| parent | 597de2849d8a0861ba0d7fca32948bdf37378eed (diff) | |
| download | coreboot-94b856ef9afaca880909d22b24d5443408c47920.tar.xz | |
FSP 1.1: Move common FSP code
Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values
associated with this common code.
BRANCH=none
BUG=None
TEST=Build and run on kunimitsu
Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/braswell/Kconfig')
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5a41056103..e6f22755ad 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -17,6 +17,10 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED + select FSP_RAM_INIT + select FSP_ROMSTAGE + select FSP_STACK + select FSP_STAGE_CACHE select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER @@ -33,11 +37,7 @@ config CPU_SPECIFIC_OPTIONS select REG_SCRIPT select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOC_INTEL_COMMON_FSP_RAM_INIT - select SOC_INTEL_COMMON_FSP_ROMSTAGE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_STACK - select SOC_INTEL_COMMON_STAGE_CACHE select SMM_TSEG select SMP select SPI_FLASH |