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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-03-04 18:32:37 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-07 17:51:32 +0000 |
| commit | 6e61c5ec00ebfac6c7e695e9eedd53a421e75894 (patch) | |
| tree | 82e5a89af8c9f69c613edcdb3be85767c0130736 /src/soc/intel/braswell/Kconfig | |
| parent | fd2d4730c66386e99e5beaa853055a5e92088dab (diff) | |
| download | coreboot-6e61c5ec00ebfac6c7e695e9eedd53a421e75894.tar.xz | |
soc/intel/braswell: Generate microcode binaries from tree
Automatically add microcode binaries from intel-microcode 3rdparty
respository for Braswell processors using Makefile.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iec57e4d5cd63b9bccc869bf178053f1c99b81b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel/braswell/Kconfig')
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5b6a9237e7..a437db2580 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -15,7 +15,6 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_IN_BLOB_REPO select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_SMI_HANDLER select NO_FIXED_XIP_ROM_SIZE |