Braswell: Add Braswell SOC support

Add the files to support the Braswell SOC.

BRANCH=none
BUG=None
TEST=Build for a Braswell platform

Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 55 insertions, 45 deletions

diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 0806bbb532..540ac84ed8 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
 subdirs-y += bootblock
 subdirs-y += microcode
 subdirs-y += romstage
+subdirs-y += ../common
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/smm
@@ -10,56 +11,63 @@ subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
-ramstage-y += memmap.c
+romstage-y += gpio_support.c
+romstage-y += iosf.c
 romstage-y += memmap.c
-ramstage-y += tsc_freq.c
 romstage-y += tsc_freq.c
-smm-y += tsc_freq.c
-ramstage-y += spi.c
-smm-y += spi.c
+
+ramstage-y += acpi.c
 ramstage-y += chip.c
+ramstage-y += cpu.c
+ramstage-$(CONFIG_ELOG) += elog.c
+ramstage-y += emmc.c
+ramstage-y += gpio.c
+ifeq ($(CONFIG_GOP_SUPPORT),n)
 ramstage-y += gfx.c
+endif
+ramstage-y += hda.c
 ramstage-y += iosf.c
-romstage-y += iosf.c
-smm-y += iosf.c
+ramstage-y += lpe.c
+ramstage-y += lpss.c
+ramstage-y += memmap.c
 ramstage-y += northcluster.c
-ramstage-y += ramstage.c
-ramstage-y += gpio.c
-romstage-y += reset.c
-ramstage-y += reset.c
-ramstage-y += cpu.c
+ramstage-y += pcie.c
 ramstage-y += pmutil.c
-smm-y += pmutil.c
-smm-y += smihandler.c
-ramstage-y += smm.c
-ramstage-y += ehci.c
-ramstage-y += xhci.c
-ramstage-y += southcluster.c
-ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
+ramstage-y += ramstage.c
 ramstage-y += sata.c
-ramstage-y += acpi.c
-ramstage-y += lpe.c
 ramstage-y += scc.c
-ramstage-y += emmc.c
-ramstage-y += lpss.c
-ramstage-y += pcie.c
 ramstage-y += sd.c
-ramstage-y += dptf.c
-ramstage-y += perf_power.c
-ramstage-y += stage_cache.c
-romstage-y += stage_cache.c
-ramstage-$(CONFIG_ELOG) += elog.c
-ramstage-y += hda.c
+ramstage-y += smm.c
+ramstage-y += southcluster.c
+ramstage-y += spi.c
+ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c
+ramstage-y += tsc_freq.c
 
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
-CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
+smm-y += pmutil.c
+smm-y += smihandler.c
+smm-y += spi.c
+smm-y += tsc_freq.c
+
+CPPFLAGS_common += -I$(src)/arch/x86/include/
+CPPFLAGS_common += -I$(src)/soc/intel/braswell/
+CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
+
+CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
+
+CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
+CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
 
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
-INTERMEDIATE:=baytrail_add_me
+INTERMEDIATE := pch_add_me
 
 ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
@@ -70,7 +78,7 @@ else
 IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
 endif
 
-baytrail_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
+pch_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
 ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 	printf "\n** WARNING **\n"
 	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
@@ -80,28 +88,30 @@ ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
 endif
 	printf "    DD         Adding Intel Firmware Descriptor\n"
+	printf "CONFIG_IFD_BIN_PATH: $(CONFIG_IFD_BIN_PATH)\n"
+	printf "IFD_BIN_PATH: $(IFD_BIN_PATH)\n"
 	dd if=$(IFD_BIN_PATH) \
 		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+	printf "CONFIG_HAVE_ME_BIN: $(CONFIG_HAVE_ME_BIN)\n"
 ifeq ($(CONFIG_HAVE_ME_BIN),y)
 	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
+	printf "CONFIG_ME_BIN_PATH: $(CONFIG_ME_BIN_PATH)\n"
 	$(objutil)/ifdtool/ifdtool \
 		-i ME:$(CONFIG_ME_BIN_PATH) \
 		$(obj)/coreboot.pre
 	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
 endif
 
-# If an MRC file is an ELF file determine the entry address and first loadable
-# section offset in the file. Subtract the offset from the entry address to
-# determine the final location.
-mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' )
-mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }')
-
-# Add memory reference code blob.
-cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin
-mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
-mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS))
-mrc.bin-type := mrc
+ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
+	printf "    IFDTOOL    Locking Management Engine\n"
+	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+else
+	printf "    IFDTOOL    Unlocking Management Engine\n"
+	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+endif
 
-PHONY += baytrail_add_me
+PHONY += pch_add_me
 
 endif