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authorLee Leahy <leroy.p.leahy@intel.com>2015-04-20 15:20:28 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2015-06-25 21:50:48 +0200
commit32471729d9ebbabe809711ec55568925c6ce2070 (patch)
treeb9f6db4e4969ee5edd6c2571e4f7612121070a9f /src/soc/intel/braswell/acpi
parent5fe62efb77a2ecfeecdcc526404712b816e74693 (diff)
downloadcoreboot-32471729d9ebbabe809711ec55568925c6ce2070.tar.xz
Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/acpi')
-rw-r--r--src/soc/intel/braswell/acpi/cpu.asl50
-rw-r--r--src/soc/intel/braswell/acpi/device_nvs.asl110
-rw-r--r--src/soc/intel/braswell/acpi/dptf/cpu.asl86
-rw-r--r--src/soc/intel/braswell/acpi/dptf/dptf.asl11
-rw-r--r--src/soc/intel/braswell/acpi/dptf/thermal.asl12
-rw-r--r--src/soc/intel/braswell/acpi/dptf/wifi.asl16
-rw-r--r--src/soc/intel/braswell/acpi/dptf/wwan.asl16
-rw-r--r--src/soc/intel/braswell/acpi/globalnvs.asl66
-rw-r--r--src/soc/intel/braswell/acpi/gpio.asl69
-rw-r--r--src/soc/intel/braswell/acpi/irqlinks.asl145
-rw-r--r--src/soc/intel/braswell/acpi/irqroute.asl6
-rw-r--r--src/soc/intel/braswell/acpi/lpc.asl42
-rw-r--r--src/soc/intel/braswell/acpi/lpe.asl6
-rw-r--r--src/soc/intel/braswell/acpi/lpss.asl24
-rw-r--r--src/soc/intel/braswell/acpi/pcie.asl109
-rw-r--r--src/soc/intel/braswell/acpi/platform.asl18
-rw-r--r--src/soc/intel/braswell/acpi/scc.asl12
-rw-r--r--src/soc/intel/braswell/acpi/sleepstates.asl2
-rw-r--r--src/soc/intel/braswell/acpi/southcluster.asl78
19 files changed, 441 insertions, 437 deletions
diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl
index 85b2014558..d487974a68 100644
--- a/src/soc/intel/braswell/acpi/cpu.asl
+++ b/src/soc/intel/braswell/acpi/cpu.asl
@@ -18,22 +18,34 @@
* Foundation, Inc.
*/
+/* CPU */
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 80
+#define DPTF_CPU_ACTIVE_AC2 70
+#define DPTF_CPU_ACTIVE_AC3 60
+#define DPTF_CPU_ACTIVE_AC4 50
+
/* These devices are created at runtime */
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-External (\_PR.CP02, DeviceObj)
-External (\_PR.CP03, DeviceObj)
+External (\_PR.CPU0, DeviceObj)
+External (\_PR.CPU1, DeviceObj)
+External (\_PR.CPU2, DeviceObj)
+External (\_PR.CPU3, DeviceObj)
+
/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
Method (PNOT)
{
If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x81) // _CST
- Notify (\_PR.CP01, 0x81) // _CST
+ Notify (\_PR.CPU0, 0x81) /* _CST */
+ Notify (\_PR.CPU1, 0x81) /* _CST */
}
If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x81) // _CST
- Notify (\_PR.CP03, 0x81) // _CST
+ Notify (\_PR.CPU2, 0x81) /* _CST */
+ Notify (\_PR.CPU3, 0x81) /* _CST */
}
}
@@ -41,12 +53,12 @@ Method (PNOT)
Method (PPCN)
{
If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x80) // _PPC
- Notify (\_PR.CP01, 0x80) // _PPC
+ Notify (\_PR.CPU0, 0x80) /* _PPC */
+ Notify (\_PR.CPU1, 0x80) /* _PPC */
}
If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x80) // _PPC
- Notify (\_PR.CP03, 0x80) // _PPC
+ Notify (\_PR.CPU2, 0x80) /* _PPC */
+ Notify (\_PR.CPU3, 0x80) /* _PPC */
}
}
@@ -54,12 +66,12 @@ Method (PPCN)
Method (TNOT)
{
If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x82) // _TPC
- Notify (\_PR.CP01, 0x82) // _TPC
+ Notify (\_PR.CPU0, 0x82) /* _TPC */
+ Notify (\_PR.CPU1, 0x82) /* _TPC */
}
If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x82) // _TPC
- Notify (\_PR.CP03, 0x82) // _TPC
+ Notify (\_PR.CPU2, 0x82) /* _TPC */
+ Notify (\_PR.CPU3, 0x82) /* _TPC */
}
}
@@ -67,10 +79,10 @@ Method (TNOT)
Method (PPKG)
{
If (LGreaterEqual (\PCNT, 4)) {
- Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03})
+ Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3})
} ElseIf (LGreaterEqual (\PCNT, 2)) {
- Return (Package() {\_PR.CP00, \_PR.CP01})
+ Return (Package() {\_PR.CPU0, \_PR.CPU1})
} Else {
- Return (Package() {\_PR.CP00})
+ Return (Package() {\_PR.CPU0})
}
}
diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl
index 1bb7d95fe3..19e4368f97 100644
--- a/src/soc/intel/braswell/acpi/device_nvs.asl
+++ b/src/soc/intel/braswell/acpi/device_nvs.asl
@@ -20,67 +20,67 @@
/* Device Enabled in ACPI Mode */
-S0EN, 8, // SDMA Enable
-S1EN, 8, // I2C1 Enable
-S2EN, 8, // I2C2 Enable
-S3EN, 8, // I2C3 Enable
-S4EN, 8, // I2C4 Enable
-S5EN, 8, // I2C5 Enable
-S6EN, 8, // I2C6 Enable
-S7EN, 8, // I2C7 Enable
-S8EN, 8, // SDMA2 Enable
-S9EN, 8, // SPI Enable
-SAEN, 8, // PWM1 Enable
-SBEN, 8, // PWM2 Enable
-SCEN, 8, // UART2 Enable
-SDEN, 8, // UART2 Enable
-C0EN, 8, // MMC Enable
-C1EN, 8, // SDIO Enable
-C2EN, 8, // SD Card Enable
-LPEN, 8, // LPE Enable
+S0EN, 8, /* SDMA Enable */
+S1EN, 8, /* I2C1 Enable */
+S2EN, 8, /* I2C2 Enable */
+S3EN, 8, /* I2C3 Enable */
+S4EN, 8, /* I2C4 Enable */
+S5EN, 8, /* I2C5 Enable */
+S6EN, 8, /* I2C6 Enable */
+S7EN, 8, /* I2C7 Enable */
+S8EN, 8, /* SDMA2 Enable */
+S9EN, 8, /* SPI Enable */
+SAEN, 8, /* PWM1 Enable */
+SBEN, 8, /* PWM2 Enable */
+SCEN, 8, /* UART2 Enable */
+SDEN, 8, /* UART2 Enable */
+C0EN, 8, /* MMC Enable */
+C1EN, 8, /* SDIO Enable */
+C2EN, 8, /* SD Card Enable */
+LPEN, 8, /* LPE Enable */
/* BAR 0 */
-S0B0, 32, // SDMA BAR0
-S1B0, 32, // I2C1 BAR0
-S2B0, 32, // I2C2 BAR0
-S3B0, 32, // I2C3 BAR0
-S4B0, 32, // I2C4 BAR0
-S5B0, 32, // I2C5 BAR0
-S6B0, 32, // I2C6 BAR0
-S7B0, 32, // I2C7 BAR0
-S8B0, 32, // SDMA2 BAR0
-S9B0, 32, // SPI BAR0
-SAB0, 32, // PWM1 BAR0
-SBB0, 32, // PWM2 BAR0
-SCB0, 32, // UART1 BAR0
-SDB0, 32, // UART2 BAR0
-C0B0, 32, // MMC BAR0
-C1B0, 32, // SDIO BAR0
-C2B0, 32, // SD Card BAR0
-LPB0, 32, // LPE BAR0
+S0B0, 32, /* SDMA BAR0 */
+S1B0, 32, /* I2C1 BAR0 */
+S2B0, 32, /* I2C2 BAR0 */
+S3B0, 32, /* I2C3 BAR0 */
+S4B0, 32, /* I2C4 BAR0 */
+S5B0, 32, /* I2C5 BAR0 */
+S6B0, 32, /* I2C6 BAR0 */
+S7B0, 32, /* I2C7 BAR0 */
+S8B0, 32, /* SDMA2 BAR0 */
+S9B0, 32, /* SPI BAR0 */
+SAB0, 32, /* PWM1 BAR0 */
+SBB0, 32, /* PWM2 BAR0 */
+SCB0, 32, /* UART1 BAR0 */
+SDB0, 32, /* UART2 BAR0 */
+C0B0, 32, /* MMC BAR0 */
+C1B0, 32, /* SDIO BAR0 */
+C2B0, 32, /* SD Card BAR0 */
+LPB0, 32, /* LPE BAR0 */
/* BAR 1 */
-S0B1, 32, // SDMA BAR1
-S1B1, 32, // I2C1 BAR1
-S2B1, 32, // I2C2 BAR1
-S3B1, 32, // I2C3 BAR1
-S4B1, 32, // I2C4 BAR1
-S5B1, 32, // I2C5 BAR1
-S6B1, 32, // I2C6 BAR1
-S7B1, 32, // I2C7 BAR1
-S8B1, 32, // SDMA2 BAR1
-S9B1, 32, // SPI BAR1
-SAB1, 32, // PWM1 BAR1
-SBB1, 32, // PWM2 BAR1
-SCB1, 32, // UART1 BAR1
-SDB1, 32, // UART2 BAR1
-C0B1, 32, // MMC BAR1
-C1B1, 32, // SDIO BAR1
-C2B1, 32, // SD Card BAR1
-LPB1, 32, // LPE BAR1
+S0B1, 32, /* SDMA BAR1 */
+S1B1, 32, /* I2C1 BAR1 */
+S2B1, 32, /* I2C2 BAR1 */
+S3B1, 32, /* I2C3 BAR1 */
+S4B1, 32, /* I2C4 BAR1 */
+S5B1, 32, /* I2C5 BAR1 */
+S6B1, 32, /* I2C6 BAR1 */
+S7B1, 32, /* I2C7 BAR1 */
+S8B1, 32, /* SDMA2 BAR1 */
+S9B1, 32, /* SPI BAR1 */
+SAB1, 32, /* PWM1 BAR1 */
+SBB1, 32, /* PWM2 BAR1 */
+SCB1, 32, /* UART1 BAR1 */
+SDB1, 32, /* UART2 BAR1 */
+C0B1, 32, /* MMC BAR1 */
+C1B1, 32, /* SDIO BAR1 */
+C2B1, 32, /* SD Card BAR1 */
+LPB1, 32, /* LPE BAR1 */
/* Extra */
-LPFW, 32, // LPE BAR2 Firmware
+LPFW, 32, /* LPE BAR2 Firmware */
diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl
index 58c1c7bea7..9b1930b926 100644
--- a/src/soc/intel/braswell/acpi/dptf/cpu.asl
+++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl
@@ -1,13 +1,13 @@
-External (\_PR.CP00._TSS, MethodObj)
-External (\_PR.CP00._TPC, MethodObj)
-External (\_PR.CP00._PTC, PkgObj)
-External (\_PR.CP00._TSD, PkgObj)
-External (\_PR.CP00._PSS, MethodObj)
-
-Device (TCPU)
+External (\_PR.CPU0._TSS, MethodObj)
+External (\_PR.CPU0._TPC, MethodObj)
+External (\_PR.CPU0._PTC, PkgObj)
+External (\_PR.CPU0._TSD, PkgObj)
+External (\_PR.CPU0._PSS, MethodObj)
+External (\_SB.DPTF.CTOK, MethodObj)
+
+Device (B0DB)
{
- Name (_HID, EISAID ("INT3401"))
- Name (_UID, 0)
+ Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */
Method (_STA)
{
@@ -24,8 +24,8 @@ Device (TCPU)
Method (_TSS)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Return (\_PR.CP00._TSS)
+ If (CondRefOf (\_PR.CPU0._TSS)) {
+ Return (\_PR.CPU0._TSS)
} Else {
Return (Package ()
{
@@ -36,8 +36,8 @@ Device (TCPU)
Method (_TPC)
{
- If (CondRefOf (\_PR.CP00._TPC)) {
- Return (\_PR.CP00._TPC)
+ If (CondRefOf (\_PR.CPU0._TPC)) {
+ Return (\_PR.CPU0._TPC)
} Else {
Return (0)
}
@@ -45,8 +45,8 @@ Device (TCPU)
Method (_PTC)
{
- If (CondRefOf (\_PR.CP00._PTC)) {
- Return (\_PR.CP00._PTC)
+ If (CondRefOf (\_PR.CPU0._PTC)) {
+ Return (\_PR.CPU0._PTC)
} Else {
Return (Package ()
{
@@ -58,8 +58,8 @@ Device (TCPU)
Method (_TSD)
{
- If (CondRefOf (\_PR.CP00._TSD)) {
- Return (\_PR.CP00._TSD)
+ If (CondRefOf (\_PR.CPU0._TSD)) {
+ Return (\_PR.CPU0._TSD)
} Else {
Return (Package ()
{
@@ -70,8 +70,8 @@ Device (TCPU)
Method (_TDL)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Store (SizeOf (\_PR.CP00._TSS ()), Local0)
+ If (CondRefOf (\_PR.CPU0._TSS)) {
+ Store (SizeOf (\_PR.CPU0._TSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@@ -98,8 +98,8 @@ Device (TCPU)
Method (_PSS)
{
- If (CondRefOf (\_PR.CP00._PSS)) {
- Return (\_PR.CP00._PSS)
+ If (CondRefOf (\_PR.CPU0._PSS)) {
+ Return (\_PR.CPU0._PSS)
} Else {
Return (Package ()
{
@@ -113,8 +113,8 @@ Device (TCPU)
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
- } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
- Store (SizeOf (\_PR.CP00._PSS ()), Local0)
+ } ElseIf (CondRefOf (\_PR.CPU0._PSS)) {
+ Store (SizeOf (\_PR.CPU0._PSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@@ -127,18 +127,52 @@ Device (TCPU)
{
Return (\_SB.MPPC)
}
-
#ifdef DPTF_CPU_CRITICAL
Method (_CRT)
{
- Return (^^CTOK (DPTF_CPU_CRITICAL))
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL))
}
#endif
#ifdef DPTF_CPU_PASSIVE
Method (_PSV)
{
- Return (^^CTOK (DPTF_CPU_PASSIVE))
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4))
}
#endif
}
diff --git a/src/soc/intel/braswell/acpi/dptf/dptf.asl b/src/soc/intel/braswell/acpi/dptf/dptf.asl
index 9ebfb8c9ce..f8d8347ac8 100644
--- a/src/soc/intel/braswell/acpi/dptf/dptf.asl
+++ b/src/soc/intel/braswell/acpi/dptf/dptf.asl
@@ -1,3 +1,4 @@
+
Device (DPTF)
{
Name (_HID, EISAID ("INT3400"))
@@ -24,7 +25,8 @@ Device (DPTF)
}
}
- /* Arg0: Buffer containing UUID
+ /*
+ * Arg0: Buffer containing UUID
* Arg1: Integer containing Revision ID of buffer format
* Arg2: Integer containing count of entries in Arg3
* Arg3: Buffer containing list of DWORD capabilities
@@ -65,9 +67,6 @@ Device (DPTF)
Return (Local0)
}
- /* Include CPU Participant */
- #include "cpu.asl"
-
/* Include Thermal Participants */
#include "thermal.asl"
@@ -75,4 +74,8 @@ Device (DPTF)
/* Include Charger Participant */
#include "charger.asl"
#endif
+
+ /* Include Network Participants */
+ #include "wifi.asl"
+ #include "wwan.asl"
}
diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl
index 7113215cd3..b123fb6d79 100644
--- a/src/soc/intel/braswell/acpi/dptf/thermal.asl
+++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl
@@ -60,12 +60,12 @@ Device (TSR0)
Method (_PSV)
{
- Return (^^CTOK (DPTF_TSR0_PASSIVE))
+ Return (CTOK (DPTF_TSR0_PASSIVE))
}
Method (_CRT)
{
- Return (^^CTOK (DPTF_TSR0_CRITICAL))
+ Return (CTOK (DPTF_TSR0_CRITICAL))
}
Name (PATC, 2)
@@ -116,12 +116,12 @@ Device (TSR1)
Method (_PSV)
{
- Return (^^CTOK (DPTF_TSR1_PASSIVE))
+ Return (CTOK (DPTF_TSR1_PASSIVE))
}
Method (_CRT)
{
- Return (^^CTOK (DPTF_TSR1_CRITICAL))
+ Return (CTOK (DPTF_TSR1_CRITICAL))
}
Name (PATC, 2)
@@ -172,12 +172,12 @@ Device (TSR2)
Method (_PSV)
{
- Return (^^CTOK (DPTF_TSR2_PASSIVE))
+ Return (CTOK (DPTF_TSR2_PASSIVE))
}
Method (_CRT)
{
- Return (^^CTOK (DPTF_TSR2_CRITICAL))
+ Return (CTOK (DPTF_TSR2_CRITICAL))
}
Name (PATC, 2)
diff --git a/src/soc/intel/braswell/acpi/dptf/wifi.asl b/src/soc/intel/braswell/acpi/dptf/wifi.asl
new file mode 100644
index 0000000000..28da69a3e4
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/dptf/wifi.asl
@@ -0,0 +1,16 @@
+Device (WIFI)
+{
+ Name (_HID, "INT3408")
+ Name (_UID, 0)
+ Name (PTYP, 0x07)
+ Name (_STR, Unicode("WIFI wireless device"))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+}
diff --git a/src/soc/intel/braswell/acpi/dptf/wwan.asl b/src/soc/intel/braswell/acpi/dptf/wwan.asl
new file mode 100644
index 0000000000..f205b8af29
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/dptf/wwan.asl
@@ -0,0 +1,16 @@
+Device (WWAN)
+{
+ Name (_HID, "INT3408")
+ Name (_UID, 0)
+ Name (PTYP, 0xF)
+ Name (_STR, Unicode("Wireless Wide Area Network"))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+}
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 36eb98f5ea..fe131f993a 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -20,9 +20,10 @@
/* Global Variables */
-Name(\PICM, 0) // IOAPIC/8259
+Name(\PICM, 0) /* IOAPIC/8259 */
-/* Global ACPI memory region. This region is used for passing information
+/*
+ * Global ACPI memory region. This region is used for passing information
* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
* Since we don't know where this will end up in memory at ACPI compile time,
* we have to fix it up in coreboot's ACPI creation phase.
@@ -34,48 +35,49 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
- OSYS, 16, // 0x00 - Operating System
- SMIF, 8, // 0x02 - SMI function
- PRM0, 8, // 0x03 - SMI function parameter
- PRM1, 8, // 0x04 - SMI function parameter
- SCIF, 8, // 0x05 - SCI function
- PRM2, 8, // 0x06 - SCI function parameter
- PRM3, 8, // 0x07 - SCI function parameter
- LCKF, 8, // 0x08 - Global Lock function for EC
- PRM4, 8, // 0x09 - Lock function parameter
- PRM5, 8, // 0x0a - Lock function parameter
- P80D, 32, // 0x0b - Debug port (IO 0x80) value
- LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
- PCNT, 8, // 0x11 - Processor count
- TPMP, 8, // 0x12 - TPM Present and Enabled
- TLVL, 8, // 0x13 - Throttle Level
- PPCM, 8, // 0x14 - Maximum P-state usable by OS
- PM1I, 32, // 0x15 - System Wake Source - PM1 Index
+ OSYS, 16, /* 0x00 - Operating System */
+ SMIF, 8, /* 0x02 - SMI function */
+ PRM0, 8, /* 0x03 - SMI function parameter */
+ PRM1, 8, /* 0x04 - SMI function parameter */
+ SCIF, 8, /* 0x05 - SCI function */
+ PRM2, 8, /* 0x06 - SCI function parameter */
+ PRM3, 8, /* 0x07 - SCI function parameter */
+ LCKF, 8, /* 0x08 - Global Lock function for EC */
+ PRM4, 8, /* 0x09 - Lock function parameter */
+ PRM5, 8, /* 0x0a - Lock function parameter */
+ P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
+ LIDS, 8, /* 0x0f - LID state (open = 1) */
+ PWRS, 8, /* 0x10 - Power State (AC = 1) */
+ PCNT, 8, /* 0x11 - Processor count */
+ TPMP, 8, /* 0x12 - TPM Present and Enabled */
+ TLVL, 8, /* 0x13 - Throttle Level */
+ PPCM, 8, /* 0x14 - Maximum P-state usable by OS */
+ PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */
+ BDID, 8, /* 0x19 - Board ID */
/* Device Config */
Offset (0x20),
- S5U0, 8, // 0x20 - Enable USB0 in S5
- S5U1, 8, // 0x21 - Enable USB1 in S5
- S3U0, 8, // 0x22 - Enable USB0 in S3
- S3U1, 8, // 0x23 - Enable USB1 in S3
- TACT, 8, // 0x24 - Thermal Active trip point
- TPSV, 8, // 0x25 - Thermal Passive trip point
- TCRT, 8, // 0x26 - Thermal Critical trip point
- DPTE, 8, // 0x27 - Enable DPTF
+ S5U0, 8, /* 0x20 - Enable USB0 in S5 */
+ S5U1, 8, /* 0x21 - Enable USB1 in S5 */
+ S3U0, 8, /* 0x22 - Enable USB0 in S3 */
+ S3U1, 8, /* 0x23 - Enable USB1 in S3 */
+ TACT, 8, /* 0x24 - Thermal Active trip point */
+ TPSV, 8, /* 0x25 - Thermal Passive trip point */
+ TCRT, 8, /* 0x26 - Thermal Critical trip point */
+ DPTE, 8, /* 0x27 - Enable DPTF */
/* Base addresses */
Offset (0x30),
- CMEM, 32, // 0x30 - CBMEM TOC
- TOLM, 32, // 0x34 - Top of Low Memory
- CBMC, 32, // 0x38 - coreboot mem console pointer
+ CMEM, 32, /* 0x30 - CBMEM TOC */
+ TOLM, 32, /* 0x34 - Top of Low Memory */
+ CBMC, 32, /* 0x38 - coreboot mem console pointer */
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
Offset (0x1000),
- #include <soc/intel/baytrail/acpi/device_nvs.asl>
+ #include <soc/intel/braswell/acpi/device_nvs.asl>
}
/* Set flag to enable USB charging in S3 */
diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl
index abe58901ca..4f1114f60e 100644
--- a/src/soc/intel/braswell/acpi/gpio.asl
+++ b/src/soc/intel/braswell/acpi/gpio.asl
@@ -21,26 +21,26 @@
#include <soc/iomap.h>
#include <soc/irq.h>
-/* SouthCluster GPIO */
-Device (GPSC)
+/* GPIO SouthWest Community */
+Device (GPSW)
{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
+ Name (_HID, "INT33FF")
+ Name (_CID, "INT33FF")
Name (_UID, 1)
Name (RBUF, ResourceTemplate()
{
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+ Memory32Fixed (ReadWrite, 0, 0x8000, RMEM)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
{
- GPIO_SC_IRQ
+ GPIO_SW_IRQ
}
})
Method (_CRS)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+ Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHWEST, RBAS)
Return (^RBUF)
}
@@ -50,26 +50,26 @@ Device (GPSC)
}
}
-/* NorthCluster GPIO */
+/* GPIO North Community */
Device (GPNC)
{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
+ Name (_HID, "INT33FF")
+ Name (_CID, "INT33FF")
Name (_UID, 2)
Name (RBUF, ResourceTemplate()
{
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+ Memory32Fixed (ReadWrite, 0, 0x8000, RMEM)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
{
- GPIO_NC_IRQ
+ GPIO_N_IRQ
}
})
Method (_CRS)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+ Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPNORTH, RBAS)
Return (^RBUF)
}
@@ -79,26 +79,55 @@ Device (GPNC)
}
}
-/* SUS GPIO */
-Device (GPSS)
+/* GPIO East Community */
+Device (GPEC)
{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
+ Name (_HID, "INT33FF")
+ Name (_CID, "INT33FF")
Name (_UID, 3)
Name (RBUF, ResourceTemplate()
{
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+ Memory32Fixed (ReadWrite, 0, 0x8000, RMEM)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
{
- GPIO_SUS_IRQ
+ GPIO_E_IRQ
}
})
Method (_CRS)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+ Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPEAST, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+/* GPIO SouthEast Community */
+Device (GPSE)
+{
+ Name (_HID, "INT33FF")
+ Name (_CID, "INT33FF")
+ Name (_UID, 4)
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x8000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
+ {
+ GPIO_SE_IRQ
+ }
+ })
+
+ Method (_CRS)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHEAST, RBAS)
Return (^RBUF)
}
diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl
index acc03f0ceb..cb45e13f0d 100644
--- a/src/soc/intel/braswell/acpi/irqlinks.asl
+++ b/src/soc/intel/braswell/acpi/irqlinks.asl
@@ -23,20 +23,20 @@ Device (LNKA)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 1)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTA)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLA, ResourceTemplate()
@@ -45,28 +45,28 @@ Device (LNKA)
})
CreateWordField(RTLA, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTA
+ /* Set the bit from PRTA */
ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
Return (RTLA)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTA)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTA, 0x80)) {
@@ -82,20 +82,20 @@ Device (LNKB)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 2)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTB)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLB, ResourceTemplate()
@@ -104,28 +104,28 @@ Device (LNKB)
})
CreateWordField(RTLB, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTB
+ /* Set the bit from PRTB */
ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
Return (RTLB)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTB)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTB, 0x80)) {
@@ -141,20 +141,20 @@ Device (LNKC)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 3)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTC)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLC, ResourceTemplate()
@@ -163,28 +163,28 @@ Device (LNKC)
})
CreateWordField(RTLC, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTC
+ /* Set the bit from PRTC */
ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
Return (RTLC)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTC)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTC, 0x80)) {
@@ -200,20 +200,20 @@ Device (LNKD)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 4)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTD)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLD, ResourceTemplate()
@@ -222,28 +222,28 @@ Device (LNKD)
})
CreateWordField(RTLD, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTD
+ /* Set the bit from PRTD */
ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
Return (RTLD)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTD)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTD, 0x80)) {
@@ -259,20 +259,20 @@ Device (LNKE)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 5)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTE)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLE, ResourceTemplate()
@@ -281,28 +281,28 @@ Device (LNKE)
})
CreateWordField(RTLE, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTE
+ /* Set the bit from PRTE */
ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
Return (RTLE)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTE)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTE, 0x80)) {
@@ -318,20 +318,20 @@ Device (LNKF)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 6)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTF)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLF, ResourceTemplate()
@@ -340,28 +340,28 @@ Device (LNKF)
})
CreateWordField(RTLF, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTF
+ /* Set the bit from PRTF */
ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
Return (RTLF)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTF)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTF, 0x80)) {
@@ -377,20 +377,20 @@ Device (LNKG)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 7)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTG)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLG, ResourceTemplate()
@@ -399,28 +399,28 @@ Device (LNKG)
})
CreateWordField(RTLG, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTG
+ /* Set the bit from PRTG */
ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
Return (RTLG)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTG)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTG, 0x80)) {
@@ -436,20 +436,20 @@ Device (LNKH)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 8)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTH)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLH, ResourceTemplate()
@@ -458,28 +458,28 @@ Device (LNKH)
})
CreateWordField(RTLH, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTH
+ /* Set the bit from PRTH */
ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
Return (RTLH)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTH)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTH, 0x80)) {
@@ -489,3 +489,4 @@ Device (LNKH)
}
}
}
+
diff --git a/src/soc/intel/braswell/acpi/irqroute.asl b/src/soc/intel/braswell/acpi/irqroute.asl
index 3a0abe4c3a..32c12baf8e 100644
--- a/src/soc/intel/braswell/acpi/irqroute.asl
+++ b/src/soc/intel/braswell/acpi/irqroute.asl
@@ -18,19 +18,19 @@
* Foundation, Inc.
*/
-// PCI Interrupt Routing
+/* PCI Interrupt Routing */
Method(_PRT)
{
If (PICM) {
Return (Package() {
#undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
+ #include <soc/intel/braswell/acpi/irq_helper.h>
PCI_DEV_PIRQ_ROUTES
})
} Else {
Return (Package() {
#define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
+ #include <soc/intel/braswell/acpi/irq_helper.h>
PCI_DEV_PIRQ_ROUTES
})
}
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index 8d48ed44f4..7fa48df862 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -19,7 +19,7 @@
* Foundation, Inc.
*/
-// Intel LPC Bus Device - 0:1f.0
+/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
{
@@ -29,7 +29,7 @@ Device (LPCB)
#include "acpi/ec.asl"
- Device (DMAC) // DMA Controller
+ Device (DMAC) /* DMA Controller */
{
Name(_HID, EISAID("PNP0200"))
Name(_CRS, ResourceTemplate()
@@ -42,7 +42,7 @@ Device (LPCB)
})
}
- Device (FWH) // Firmware Hub
+ Device (FWH) /* Firmware Hub */
{
Name (_HID, EISAID("INT0800"))
Name (_CRS, ResourceTemplate()
@@ -56,9 +56,9 @@ Device (LPCB)
Name (_HID, EISAID("PNP0103"))
Name (_CID, 0x010CD041)
- Method (_STA, 0) // Device Status
+ Method (_STA, 0) /* Device Status */
{
- Return (0xf) // Enable and show device
+ Return (0xf) /* Enable and show device */
}
Name(_CRS, ResourceTemplate()
@@ -67,7 +67,7 @@ Device (LPCB)
})
}
- Device(PIC) // 8259 Interrupt Controller
+ Device(PIC) /* 8259 Interrupt Controller */
{
Name(_HID,EISAID("PNP0000"))
Name(_CRS, ResourceTemplate()
@@ -93,20 +93,20 @@ Device (LPCB)
})
}
- Device(LDRC) // LPC device: Resource consumption
+ Device(LDRC) /* LPC device: Resource consumption */
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 2)
Name (RBUF, ResourceTemplate()
{
- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+ IO (Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+ IO (Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+ IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
})
Method (_CRS, 0, NotSerialized)
@@ -115,18 +115,20 @@ Device (LPCB)
}
}
- Device (RTC) // Real Time Clock
+ Device (RTC) /* Real Time Clock */
{
Name (_HID, EISAID("PNP0B00"))
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x70, 0x70, 1, 8)
-// Disable as Windows doesn't like it, and systems don't seem to use it.
-// IRQNoFlags() { 8 }
+/*
+ * Disable as Windows doesn't like it, and systems don't seem to use it.
+ * IRQNoFlags() { 8 }
+ */
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TIMR) /* Intel 8254 timer */
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
@@ -137,11 +139,11 @@ Device (LPCB)
})
}
- // Include mainboard's superio.asl file.
+ /* Include mainboard's superio.asl file. */
#include "acpi/superio.asl"
#ifdef ENABLE_TPM
- Device (TPM) // Trusted Platform Module
+ Device (TPM) /* Trusted Platform Module */
{
Name(_HID, EISAID("IFX0102"))
Name(_CID, 0x310cd041)
diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl
index 57fa4659b4..001e63d64d 100644
--- a/src/soc/intel/braswell/acpi/lpe.asl
+++ b/src/soc/intel/braswell/acpi/lpe.asl
@@ -20,10 +20,10 @@
Device (LPEA)
{
- Name (_HID, "80860F28")
- Name (_CID, "80860F28")
+ Name (_HID, "808622A8")
+ Name (_CID, "808622A8")
Name (_UID, 1)
- Name (_DDN, "Low Power Audio Controller")
+ Name (_DDN, "Intel(R) Low Power Audio Controller - 808622A8")
Name (_PR0, Package () { PLPE })
Name (RBUF, ResourceTemplate()
diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl
index 2591aa1d9b..ed1ba99bff 100644
--- a/src/soc/intel/braswell/acpi/lpss.asl
+++ b/src/soc/intel/braswell/acpi/lpss.asl
@@ -84,7 +84,7 @@ Device (SDM2)
Device (I2C1)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 1)
Name (_DDN, "I2C Controller #1")
@@ -143,7 +143,7 @@ Device (I2C1)
Device (I2C2)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 2)
Name (_DDN, "I2C Controller #2")
@@ -202,7 +202,7 @@ Device (I2C2)
Device (I2C3)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 3)
Name (_DDN, "I2C Controller #3")
@@ -261,7 +261,7 @@ Device (I2C3)
Device (I2C4)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 4)
Name (_DDN, "I2C Controller #4")
@@ -320,7 +320,7 @@ Device (I2C4)
Device (I2C5)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 5)
Name (_DDN, "I2C Controller #5")
@@ -379,7 +379,7 @@ Device (I2C5)
Device (I2C6)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 6)
Name (_DDN, "I2C Controller #6")
@@ -438,7 +438,7 @@ Device (I2C6)
Device (I2C7)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 7)
Name (_DDN, "I2C Controller #7")
@@ -497,7 +497,7 @@ Device (I2C7)
Device (SPI1)
{
- Name (_HID, "80860F0E")
+ Name (_HID, "8086228E")
Name (_UID, 1)
Name (_DDN, "SPI Controller #2")
@@ -550,7 +550,7 @@ Device (SPI1)
Device (PWM1)
{
- Name (_HID, "80860F09")
+ Name (_HID, "80862288")
Name (_UID, 1)
Name (_DDN, "PWM Controller #1")
@@ -578,7 +578,7 @@ Device (PWM1)
Device (PWM2)
{
- Name (_HID, "80860F09")
+ Name (_HID, "80862288")
Name (_UID, 2)
Name (_DDN, "PWM Controller #2")
@@ -606,7 +606,7 @@ Device (PWM2)
Device (UAR1)
{
- Name (_HID, "80860F0A")
+ Name (_HID, "8086228A")
Name (_UID, 1)
Name (_DDN, "HS-UART Controller #1")
@@ -659,7 +659,7 @@ Device (UAR1)
Device (UAR2)
{
- Name (_HID, "80860F0A")
+ Name (_HID, "8086228A")
Name (_UID, 2)
Name (_DDN, "HS-UART Controller #2")
diff --git a/src/soc/intel/braswell/acpi/pcie.asl b/src/soc/intel/braswell/acpi/pcie.asl
deleted file mode 100644
index c3f70cc698..0000000000
--- a/src/soc/intel/braswell/acpi/pcie.asl
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* Intel SOC PCIe support */
-
-Device (RP01)
-{
- Name (_ADR, 0x001c0000)
-
- Method (_PRT)
- {
- If (PICM) {
- Return (Package() {
- #undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
- })
- } Else {
- Return (Package() {
- #define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
- })
- }
- }
-}
-
-Device (RP02)
-{
- Name (_ADR, 0x001c0001)
-
- Method (_PRT)
- {
- If (PICM) {
- Return (Package() {
- #undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
- })
- } Else {
- Return (Package() {
- #define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
- })
- }
- }
-}
-
-Device (RP03)
-{
- Name (_ADR, 0x001c0002)
-
- Method (_PRT)
- {
- If (PICM) {
- Return (Package() {
- #undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
- })
- } Else {
- Return (Package() {
- #define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
- })
- }
- }
-}
-
-Device (RP04)
-{
- Name (_ADR, 0x001c0003)
-
- Method (_PRT)
- {
- If (PICM) {
- Return (Package() {
- #undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
- })
- } Else {
- Return (Package() {
- #define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
- })
- }
- }
-}
diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl
index 6c27ec31c0..33be9ee98e 100644
--- a/src/soc/intel/braswell/acpi/platform.asl
+++ b/src/soc/intel/braswell/acpi/platform.asl
@@ -23,8 +23,8 @@
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
- APMC, 8, // APM command
- APMS, 8 // APM status
+ APMC, 8, /* APM command */
+ APMS, 8 /* APM status */
}
/* Port 80 POST */
@@ -38,12 +38,13 @@ Field (POST, ByteAcc, Lock, Preserve)
/* SMI I/O Trap */
Method(TRAP, 1, Serialized)
{
- Store (Arg0, SMIF) // SMI Function
- Store (0, TRP0) // Generate trap
- Return (SMIF) // Return value of SMI handler
+ Store (Arg0, SMIF) /* SMI Function */
+ Store (0, TRP0) /* Generate trap */
+ Return (SMIF) /* Return value of SMI handler */
}
-/* The _PIC method is called by the OS to choose between interrupt
+/*
+ * The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
@@ -52,11 +53,12 @@ Method(TRAP, 1, Serialized)
Method(_PIC, 1)
{
- // Remember the OS' IRQ routing choice.
+ /* Remember the OS' IRQ routing choice. */
Store(Arg0, PICM)
}
-/* The _PTS method (Prepare To Sleep) is called before the OS is
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl
index 3bf3f39fa7..3034d25f58 100644
--- a/src/soc/intel/braswell/acpi/scc.asl
+++ b/src/soc/intel/braswell/acpi/scc.asl
@@ -135,18 +135,18 @@ Device (SDIO)
Device (SDCD)
{
- Name (_HID, "80860F16")
+ Name (_HID, "INT33BB")
Name (_CID, "PNP0D40")
Name (_UID, 3)
Name (_DDN, "SD Card Controller")
Name (RBUF, ResourceTemplate()
{
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- SCC_SD_IRQ
- }
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)
+ Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {SCC_SD_IRQ} /* SD Card IRQ */
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 10000, "\\_SB.GPSE", 0, ResourceConsumer, , )
+ {SDCARD_CD} /* SE81 */
})
Method (_CRS)
diff --git a/src/soc/intel/braswell/acpi/sleepstates.asl b/src/soc/intel/braswell/acpi/sleepstates.asl
index fef196e1f8..8da76b9c07 100644
--- a/src/soc/intel/braswell/acpi/sleepstates.asl
+++ b/src/soc/intel/braswell/acpi/sleepstates.asl
@@ -19,7 +19,7 @@
*/
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
-// Name(\_S1, Package(){0x1,0x1,0x0,0x0})
Name(\_S3, Package(){0x5,0x5,0x0,0x0})
Name(\_S4, Package(){0x6,0x6,0x0,0x0})
Name(\_S5, Package(){0x7,0x7,0x0,0x0})
+
diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index a985f15b85..25e0bd8dc7 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -23,16 +23,16 @@
Scope(\)
{
- // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
+ /* IO-Trap at 0x800. This is the ACPI->SMI communication interface. */
OperationRegion(IO_T, SystemIO, 0x800, 0x10)
Field(IO_T, ByteAcc, NoLock, Preserve)
{
Offset(0x8),
- TRP0, 8 // IO-Trap at 0x808
+ TRP0, 8 /* IO-Trap at 0x808 */
}
- // Intel Legacy Block
+ /* Intel Legacy Block */
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Field (ILBS, AnyAcc, NoLock, Preserve)
{
@@ -48,8 +48,8 @@ Scope(\)
}
}
-Name(_HID,EISAID("PNP0A08")) // PCIe
-Name(_CID,EISAID("PNP0A03")) // PCI
+Name(_HID,EISAID("PNP0A08")) /* PCIe */
+Name(_CID,EISAID("PNP0A03")) /* PCI */
Name(_ADR, 0)
Name(_BBN, 0)
@@ -58,126 +58,125 @@ Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
- // Bus Numbers
+ /* Bus Numbers */
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
- // IO Region 0
+ /* IO Region 0 */
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
- // PCI Config Space
+ /* PCI Config Space */
Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
- // IO Region 1
+ /* IO Region 1 */
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
- // VGA memory (0xa0000-0xbffff)
+ /* VGA memory (0xa0000-0xbffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
0x00020000,,, ASEG)
- // OPROM reserved (0xc0000-0xc3fff)
+ /* OPROM reserved (0xc0000-0xc3fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
0x00004000,,, OPR0)
- // OPROM reserved (0xc4000-0xc7fff)
+ /* OPROM reserved (0xc4000-0xc7fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
0x00004000,,, OPR1)
- // OPROM reserved (0xc8000-0xcbfff)
+ /* OPROM reserved (0xc8000-0xcbfff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
0x00004000,,, OPR2)
- // OPROM reserved (0xcc000-0xcffff)
+ /* OPROM reserved (0xcc000-0xcffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
0x00004000,,, OPR3)
- // OPROM reserved (0xd0000-0xd3fff)
+ /* OPROM reserved (0xd0000-0xd3fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
0x00004000,,, OPR4)
- // OPROM reserved (0xd4000-0xd7fff)
+ /* OPROM reserved (0xd4000-0xd7fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
0x00004000,,, OPR5)
- // OPROM reserved (0xd8000-0xdbfff)
+ /* OPROM reserved (0xd8000-0xdbfff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
0x00004000,,, OPR6)
- // OPROM reserved (0xdc000-0xdffff)
+ /* OPROM reserved (0xdc000-0xdffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
0x00004000,,, OPR7)
- // BIOS Extension (0xe0000-0xe3fff)
+ /* BIOS Extension (0xe0000-0xe3fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
0x00004000,,, ESG0)
- // BIOS Extension (0xe4000-0xe7fff)
+ /* BIOS Extension (0xe4000-0xe7fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
0x00004000,,, ESG1)
- // BIOS Extension (0xe8000-0xebfff)
+ /* BIOS Extension (0xe8000-0xebfff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
0x00004000,,, ESG2)
- // BIOS Extension (0xec000-0xeffff)
+ /* BIOS Extension (0xec000-0xeffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000ec000, 0x000effff, 0x00000000,
0x00004000,,, ESG3)
- // System BIOS (0xf0000-0xfffff)
+ /* System BIOS (0xf0000-0xfffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+ /* PCI Memory Region (Top of memory-0xfeafffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000,,, PMEM)
+ 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
+ 0x00100000,,, PMEM)
- // TPM Area (0xfed40000-0xfed44fff)
+ /* TPM Area (0xfed40000-0xfed44fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
0x00005000,,, TPMR)
})
- // Update PCI resource area
+ /* Update PCI resource area */
CreateDwordField(MCRS, PMEM._MIN, PMIN)
CreateDwordField(MCRS, PMEM._MAX, PMAX)
CreateDwordField(MCRS, PMEM._LEN, PLEN)
- // TOLM is BMBOUND accessible from IOSF so is saved in NVS
+ /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
Store (\TOLM, PMIN)
- Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
Add (Subtract (PMAX, PMIN), 1, PLEN)
Return (MCRS)
@@ -200,7 +199,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
})
- // Current Resource Settings
+ /* Current Resource Settings */
Method (_CRS, 0, Serialized)
{
Return(PDRS)
@@ -245,29 +244,26 @@ Device (IOSF)
}
}
-// LPC Bridge 0:1f.0
+/* LPC Bridge 0:1f.0 */
#include "lpc.asl"
-// USB XHCI 0:14.0
+/* USB XHCI 0:14.0 */
#include "xhci.asl"
-// IRQ routing for each PCI device
+/* IRQ routing for each PCI device */
#include "irqroute.asl"
-// PCI Express Ports 0:1c.x
-#include "pcie.asl"
-
Scope (\_SB)
{
- // GPIO Devices
+ /* GPIO Devices */
#include "gpio.asl"
- // LPSS Devices
+ /* LPSS Devices */
#include "lpss.asl"
- // SCC Devices
+ /* SCC Devices */
#include "scc.asl"
- // LPE Device
+ /* LPE Device */
#include "lpe.asl"
}