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authorLee Leahy <leroy.p.leahy@intel.com>2015-04-20 15:20:28 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2015-06-25 21:50:48 +0200
commit32471729d9ebbabe809711ec55568925c6ce2070 (patch)
treeb9f6db4e4969ee5edd6c2571e4f7612121070a9f /src/soc/intel/braswell/bootblock
parent5fe62efb77a2ecfeecdcc526404712b816e74693 (diff)
downloadcoreboot-32471729d9ebbabe809711ec55568925c6ce2070.tar.xz
Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/bootblock')
-rw-r--r--src/soc/intel/braswell/bootblock/Makefile.inc2
-rw-r--r--src/soc/intel/braswell/bootblock/bootblock.c9
-rw-r--r--src/soc/intel/braswell/bootblock/timestamp.inc7
3 files changed, 12 insertions, 6 deletions
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
index 3a4025198c..17d1ee8c5a 100644
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ b/src/soc/intel/braswell/bootblock/Makefile.inc
@@ -1 +1 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
+chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index 6d31add508..f98f694f41 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -2,13 +2,14 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
@@ -54,10 +55,12 @@ static void setup_mmconfig(void)
{
uint32_t reg;
- /* Set up the MMCONF range. The register lives in the BUNIT. The
+ /*
+ * Set up the MMCONF range. The register lives in the BUNIT. The
* IO variant of the config access needs to be used initially to
* properly configure as the IOSF access registers live in PCI
- * config space. */
+ * config space.
+ */
reg = 0;
/* Clear the extended register. */
pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
diff --git a/src/soc/intel/braswell/bootblock/timestamp.inc b/src/soc/intel/braswell/bootblock/timestamp.inc
index 3db5c35c4d..e5041326ee 100644
--- a/src/soc/intel/braswell/bootblock/timestamp.inc
+++ b/src/soc/intel/braswell/bootblock/timestamp.inc
@@ -1,6 +1,8 @@
-/* Store the initial timestamp for booting in mmx registers. This works
+/*
+ * Store the initial timestamp for booting in mmx registers. This works
* because the bootblock isn't being compiled with MMX support so mm0 and
- * mm1 will be preserved into romstage. */
+ * mm1 will be preserved into romstage.
+ */
.code32
.global stash_timestamp
@@ -16,3 +18,4 @@ stash_timestamp:
/* Restore the BIST value to %eax */
movl %ebp, %eax
+