diff options
| author | fdurairx <felixx.durairaj@intel.com> | 2015-08-21 15:36:53 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:34:06 +0100 |
| commit | aff502e87ae57fa2dc09367d00f143b6befb9530 (patch) | |
| tree | 53476f7b39033ed036b7a7bf784e2410c24d7381 /src/soc/intel/braswell/include | |
| parent | 71c60ca4821f9ebd51066b2fb4166fd974755666 (diff) | |
| download | coreboot-aff502e87ae57fa2dc09367d00f143b6befb9530.tar.xz | |
soc/braswell: Fix DSP clock
The codec clock frequency was incorrectly set to 25MHz.
The only available frequency is 19.2MHz through external clock and PLL.
Original-Reviewed-on: https://chromium-review.googlesource.com/295768
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5
Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com>
Reviewed-on: https://review.coreboot.org/12732
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/braswell/include')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/pm.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9e527e1b78..ec10101b5b 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -116,8 +116,8 @@ #define PLT_CLK_CTL_3 0x6c #define PLT_CLK_CTL_4 0x70 #define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_SRC_XTAL (0x0 << 2) +# define CLK_SRC_PLL (0x1 << 2) # define CLK_CTL_D3_LPE (0x0 << 0) # define CLK_CTL_ON (0x1 << 0) # define CLK_CTL_OFF (0x2 << 0) |