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authorShobhit Srivastava <shobhit.srivastava@intel.com>2015-08-10 11:48:23 +0530
committerMartin Roth <martinroth@google.com>2016-01-27 23:59:39 +0100
commit97f09c3f191f3dad474d5c1fd56682001095703e (patch)
treec30fa1d91c83eab05ed90ec9f64053822d9c07ae /src/soc/intel/braswell/include
parentfc5489fc5e620adf3ec9f3d692444aa4c2b3801e (diff)
downloadcoreboot-97f09c3f191f3dad474d5c1fd56682001095703e.tar.xz
soc/braswell: Fix leakage on V1P8S rail
Tristate MMC1_RCLK pin to fix leakage on V1P8S rail. Original-Reviewed-on: https://chromium-review.googlesource.com/292043 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/12730 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/braswell/include')
-rw-r--r--src/soc/intel/braswell/include/soc/gpio.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 4ab6592498..c7bfb65d65 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -105,6 +105,7 @@
#define MMC1_D5_MMIO_OFFSET GPIO_OFFSET(65)
#define MMC1_D6_MMIO_OFFSET GPIO_OFFSET(63)
#define MMC1_D7_MMIO_OFFSET GPIO_OFFSET(68)
+#define MMC1_RCLK_OFFSET GPIO_OFFSET(69)
#define HV_DDI2_DDC_SDA_MMIO_OFFSET GPIO_OFFSET(62)
#define HV_DDI2_DDC_SCL_MMIO_OFFSET GPIO_OFFSET(67)
#define CFIO_139_MMIO_OFFSET GPIO_OFFSET(64)