diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2017-03-22 16:33:36 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-25 18:59:51 +0000 |
| commit | 3fa80a9c6f44362e53d33d09da1875a42b98b30f (patch) | |
| tree | ed4fbc3ca16a7befa84fa8f98e53a91fc3cbcfbb /src/soc/intel/braswell/include | |
| parent | ad8669ef30743489909cd07be7759b29cf1dbe30 (diff) | |
| download | coreboot-3fa80a9c6f44362e53d33d09da1875a42b98b30f.tar.xz | |
soc/intel/braswell: Put SERIRQ in quiet mode
Cherry-pick from Chromium commit 1568761.
Original-Change-Id: If459c3cab8fb7ca13d8bff3173a94855ec2e2810
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Change-Id: Ibb2e6d316adcfcc0d56d242501aac9c4c0bbdf62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/include')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/lpc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h index 93ece3df87..d842274583 100644 --- a/src/soc/intel/braswell/include/soc/lpc.h +++ b/src/soc/intel/braswell/include/soc/lpc.h @@ -30,6 +30,9 @@ #define UART_CONT 0x80 #define RCBA 0xf0 +/* Memory Mapped IO in LPC bridge */ +#define SCNT 0x10 +#define SCNT_MODE (1 << 7) /* When cleared, SERIRQ is in quiet mode */ #define RID_A_STEPPING_START 1 #define RID_B_STEPPING_START 5 |