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| author | Divagar Mohandass <divagar.mohandass@intel.com> | 2016-02-08 16:09:21 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-08 21:07:53 +0000 |
| commit | 0c68530f15df0f027adb664cca0c3fcf0de2233a (patch) | |
| tree | 30b5caa75a5c7ac594b0bcd0d2fe44efa6bac005 /src/soc/intel/braswell/include | |
| parent | 77c01e1f2f16bc24a45e68b0c413e510dc19a756 (diff) | |
| download | coreboot-0c68530f15df0f027adb664cca0c3fcf0de2233a.tar.xz | |
soc/intel/braswell: Add I2C clock config options
Cherry-pick from Chromium commit e3c1ec2.
This change includes
- FSP config parameters to configure I2C clock speed.
- Options are 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz and default is 400Khz.
Original-Change-Id: Iab2bf3997102908583078f5f1d185d6c66561390
Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/include')
0 files changed, 0 insertions, 0 deletions