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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-13 22:16:25 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-18 15:25:35 +0000 |
| commit | 8950cfb66f8f1fd4b047fbef2347134be0aeacec (patch) | |
| tree | 57943bfb4f8d74c2d1a4bfbd2a9813ac27e510dd /src/soc/intel/braswell/pcie.c | |
| parent | 4af4e7f06eddad71f86eda3e401967e79d3a9ddb (diff) | |
| download | coreboot-8950cfb66f8f1fd4b047fbef2347134be0aeacec.tar.xz | |
soc/intel: Use config_of()
Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Diffstat (limited to 'src/soc/intel/braswell/pcie.c')
| -rw-r--r-- | src/soc/intel/braswell/pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 6e387d1d6b..dc779bbb80 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -141,13 +141,13 @@ static void pcie_enable(struct device *dev) printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (is_first_port(dev)) { - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = config_of(dev); uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); pll_en_off = !!(reg & PLL_OFF_EN); strpfusecfg = pci_read_config32(dev, STRPFUSECFG); - if (config && config->pcie_wake_enable) + if (config->pcie_wake_enable) southcluster_smm_save_param( SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); } |