diff options
author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:20:26 -0500 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:32:09 +0200 |
commit | 1b6196dec95e12ae44b5cfe62073c3dcd3f52686 (patch) | |
tree | cee76a83606e8d76939225c01003b2240c4ce3cd /src/soc/intel/braswell/romstage/romstage.c | |
parent | f5cfaa39342bed7dbf3abe19486089c4cf8a4561 (diff) | |
download | coreboot-1b6196dec95e12ae44b5cfe62073c3dcd3f52686.tar.xz |
soc/intel/braswell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Ia3860fe9e5229917881696e08418c3fd5fb64ecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/braswell/romstage/romstage.c')
-rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 5f2a1cefcf..95880e8159 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -137,17 +137,16 @@ struct chipset_power_state *fill_power_state(void) int chipset_prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ - int prev_sleep_state = SLEEP_STATE_S0; + int prev_sleep_state = ACPI_S0; if (ps->pm1_sts & WAK_STS) { - switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { - #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - case SLP_TYP_S3: - prev_sleep_state = SLEEP_STATE_S3; + switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { + case ACPI_S3: + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + prev_sleep_state = ACPI_S3; break; - #endif - case SLP_TYP_S5: - prev_sleep_state = SLEEP_STATE_S5; + case ACPI_S5: + prev_sleep_state = ACPI_S5; break; } @@ -156,7 +155,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps) } if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) - prev_sleep_state = SLEEP_STATE_S5; + prev_sleep_state = ACPI_S5; return prev_sleep_state; } |