diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2017-03-21 22:34:01 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-25 18:59:35 +0000 |
| commit | ad8669ef30743489909cd07be7759b29cf1dbe30 (patch) | |
| tree | 2cb47e283adf1c7d8f16c55eb226636c2bb969e7 /src/soc/intel/braswell/scc.c | |
| parent | aec5e663eb8581aeaadd55661c37bde948a7015e (diff) | |
| download | coreboot-ad8669ef30743489909cd07be7759b29cf1dbe30.tar.xz | |
soc/intel/braswell: Populate NVS SCC BAR1
Cherry-pick from Chromium commit f92d7be.
This BAR is used in _PS0 and _PS3 methods and is used by kernel driver to put
SD controller in D3
Original-Change-Id: Iae4722cb222f61e96948265f57d6b522065853d9
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/scc.c')
| -rw-r--r-- | src/soc/intel/braswell/scc.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 3172b73247..6538c5cda0 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -42,7 +42,10 @@ void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); if (bar) - gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; + gnvs->dev.scc_bar0[nvs_index] = bar->base; + bar = find_resource(dev, PCI_BASE_ADDRESS_2); + if (bar) + gnvs->dev.scc_bar1[nvs_index] = bar->base; /* Device is enabled in ACPI mode */ gnvs->dev.scc_en[nvs_index] = 1; |