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authorLee Leahy <leroy.p.leahy@intel.com>2015-05-05 15:07:29 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2015-05-23 01:40:57 +0200
commit77ff0b1a01d3d640be55d301b2fcf09a3f840ffe (patch)
treec745968f84ca4638f3a27881a5ee3943cf39773f /src/soc/intel/braswell/sd.c
parentb5ad827ee584a960212ae983e30cd1a0b18c55a5 (diff)
downloadcoreboot-77ff0b1a01d3d640be55d301b2fcf09a3f840ffe.tar.xz
Braswell: Use Baytrail as Comparison Base
Add baytrail source for comparison with Braswell. BRANCH=none BUG=None TEST=None Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/sd.c')
-rw-r--r--src/soc/intel/braswell/sd.c70
1 files changed, 70 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c
new file mode 100644
index 0000000000..577469d3aa
--- /dev/null
+++ b/src/soc/intel/braswell/sd.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <reg_script.h>
+
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include "chip.h"
+
+#define CAP_OVERRIDE_LOW 0xa0
+#define CAP_OVERRIDE_HIGH 0xa4
+# define USE_CAP_OVERRIDES (1 << 31)
+
+static void sd_init(device_t dev)
+{
+ struct soc_intel_baytrail_config *config = dev->chip_info;
+
+ if (config == NULL)
+ return;
+
+ if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) {
+ printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n");
+ pci_write_config32(dev, CAP_OVERRIDE_LOW,
+ config->sdcard_cap_low);
+ pci_write_config32(dev, CAP_OVERRIDE_HIGH,
+ config->sdcard_cap_high | USE_CAP_OVERRIDES);
+ }
+
+ if (config->scc_acpi_mode)
+ scc_enable_acpi_mode(dev, SCC_SD_CTL, SCC_NVS_SD);
+}
+
+static const struct device_operations device_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sd_init,
+ .enable = NULL,
+ .scan_bus = NULL,
+ .ops_pci = &soc_pci_ops,
+};
+
+static const struct pci_driver southcluster __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = SD_DEVID,
+};