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| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:20:26 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:32:09 +0200 |
| commit | 1b6196dec95e12ae44b5cfe62073c3dcd3f52686 (patch) | |
| tree | cee76a83606e8d76939225c01003b2240c4ce3cd /src/soc/intel/braswell/smihandler.c | |
| parent | f5cfaa39342bed7dbf3abe19486089c4cf8a4561 (diff) | |
| download | coreboot-1b6196dec95e12ae44b5cfe62073c3dcd3f52686.tar.xz | |
soc/intel/braswell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Ia3860fe9e5229917881696e08418c3fd5fb64ecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/braswell/smihandler.c')
| -rw-r--r-- | src/soc/intel/braswell/smihandler.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 760fba3c8c..0f5c7c98c3 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -146,15 +146,15 @@ static void southbridge_smi_sleep(void) /* Figure out SLP_TYP */ reg32 = inl(pmbase + PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); - slp_typ = (reg32 >> 10) & 7; + slp_typ = acpi_sleep_from_pm1(reg32); /* Do any mainboard sleep handling */ - mainboard_smi_sleep(slp_typ-2); + mainboard_smi_sleep(slp_typ); #if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ - if (slp_typ >= 5) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); + if (slp_typ >= ACPI_S3) + elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); #endif /* Clear pending GPE events */ clear_gpe_status(); @@ -162,22 +162,22 @@ static void southbridge_smi_sleep(void) /* Next, do the deed. */ switch (slp_typ) { - case SLP_TYP_S0: + case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; - case SLP_TYP_S1: + case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; - case SLP_TYP_S3: + case ACPI_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); /* Invalidate the cache before going to S3 */ wbinvd(); break; - case SLP_TYP_S4: + case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; - case SLP_TYP_S5: + case ACPI_S5: printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ @@ -195,7 +195,7 @@ static void southbridge_smi_sleep(void) read32((void *)(0xfed88000 + 0x0200))); /* Tri-state specific GPIOS to avoid leakage during S3/S5 */ - if ((slp_typ == SLP_TYP_S3) || (slp_typ == SLP_TYP_S5)) + if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) tristate_gpios(PAD_CONTROL_REG0_TRISTATE); /* @@ -206,7 +206,7 @@ static void southbridge_smi_sleep(void) enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ - if (slp_typ > 1) + if (slp_typ >= ACPI_S3) hlt(); /* |