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| author | Frans Hendriks <fhendriks@eltan.com> | 2018-12-05 15:24:48 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-06 11:59:52 +0000 |
| commit | bd5233eb3dbe2a7e3a0369ef13d4851062c347bd (patch) | |
| tree | 9b8689c6732527e3223d739cdbbe56b486903e7e /src/soc/intel/braswell/southcluster.c | |
| parent | 4f4322dd68575402e099e2dfda057687388f064e (diff) | |
| download | coreboot-bd5233eb3dbe2a7e3a0369ef13d4851062c347bd.tar.xz | |
src/soc/intel/braswell/southcluster.c: Config i8254 timer
ISA timer is not configured.
Add call setup_i8254().
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: If45c4975d147f28a456198ea290efba1c8b0464b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel/braswell/southcluster.c')
| -rw-r--r-- | src/soc/intel/braswell/southcluster.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 0c88004323..6ea2ea9aae 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -4,6 +4,7 @@ * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +26,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <pc80/i8254.h> #include <romstage_handoff.h> #include <soc/acpi.h> #include <soc/iomap.h> @@ -182,6 +184,8 @@ static void sc_init(struct device *dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } + /* Initialize i8254 timers */ + setup_i8254(); } /* |