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authorArthur Heymans <arthur@aheymans.xyz>2019-10-13 23:26:36 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-12-05 17:59:29 +0000
commit68b6eb78d2b86d43d3d285a88a686de20751cb81 (patch)
tree306f4685b828b6a6e1fec50d988dd8113117fc6d /src/soc/intel/braswell/southcluster.c
parent53486a0be0f4c8a9647158b91fb82cb951b07297 (diff)
downloadcoreboot-68b6eb78d2b86d43d3d285a88a686de20751cb81.tar.xz
soc/intel/braswell: Use common sb code for SPI lockdown configuration
This removes the weakly linked function to configure the SPI lockdown. Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/southcluster.c')
-rw-r--r--src/soc/intel/braswell/southcluster.c22
1 files changed, 7 insertions, 15 deletions
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index c233dc8172..8b13fd0e82 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -42,6 +42,7 @@
#include <soc/spi.h>
#include <spi-generic.h>
#include <stdint.h>
+#include <southbridge/intel/common/spi.h>
static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode)
{
@@ -608,13 +609,6 @@ static const struct pci_driver southcluster __pci_driver = {
.device = LPC_DEVID,
};
-int __weak mainboard_get_spi_config(struct spi_config *cfg)
-{
- printk(BIOS_SPEW, "%s/%s (0x%p)\n",
- __FILE__, __func__, (void *)cfg);
- return -1;
-}
-
static void finalize_chipset(void *unused)
{
void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
@@ -622,7 +616,7 @@ static void finalize_chipset(void *unused)
void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2);
void *etr = (void *)(PMC_BASE_ADDRESS + ETR);
uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS;
- struct spi_config cfg;
+ struct vscc_config cfg;
printk(BIOS_SPEW, "%s/%s (0x%p)\n",
__FILE__, __func__, unused);
@@ -639,14 +633,12 @@ static void finalize_chipset(void *unused)
/* Set the CF9 lock. */
write32(etr, read32(etr) | CF9LOCK);
- if (mainboard_get_spi_config(&cfg) < 0) {
- printk(BIOS_DEBUG, "No SPI lockdown configuration.\n");
+ spi_finalize_ops();
+ write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN);
+
+ if (mainboard_get_spi_vscc_config(&cfg) < 0) {
+ printk(BIOS_DEBUG, "No SPI VSCC configuration.\n");
} else {
- write16(spi + PREOP, cfg.preop);
- write16(spi + OPTYPE, cfg.optype);
- write32(spi + OPMENU0, cfg.opmenu[0]);
- write32(spi + OPMENU1, cfg.opmenu[1]);
- write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN);
write32(spi + UVSCC, cfg.uvscc);
write32(spi + LVSCC, cfg.lvscc | VCL);
}