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authorLee Leahy <leroy.p.leahy@intel.com>2017-03-16 17:49:42 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-17 02:36:36 +0100
commitd94cff6ab26d482554309041a9317cc3bf5e4b02 (patch)
treea09902883736f6eca89e96e53642ce944ff0401b /src/soc/intel/braswell/spi.c
parent1072e7dcc30895f850143450504b78a4135978b6 (diff)
downloadcoreboot-d94cff6ab26d482554309041a9317cc3bf5e4b02.tar.xz
soc/intel/braswell: Fix most of the issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl: ERROR: that open brace { should be on the previous line ERROR: return is not a function, parentheses are not required WARNING: braces {} are not necessary for any arm of this statement WARNING: line over 80 characters WARNING: braces {} are not necessary for single statement blocks WARNING: Avoid unnecessary line continuations WARNING: break is not useful after a goto or return WARNING: else is not generally useful after a break or return False positives are generated by checkpatch for the following test: ERROR: Macros with complex values should be enclosed in parentheses TEST=Build for cyan Change-Id: I19048895145b138a63100b29f829ff446ff71b58 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18871 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/braswell/spi.c')
-rw-r--r--src/soc/intel/braswell/spi.c68
1 files changed, 34 insertions, 34 deletions
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index 514e70e418..5121be016b 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -350,43 +350,43 @@ static int spi_setup_opcode(spi_transaction *trans)
optypes = (optypes & 0xfffc) | (trans->type & 0x3);
writew_(optypes, cntlr.optype);
return 0;
- } else {
- /* The lock is on. See if what we need is on the menu. */
- uint8_t optype;
- uint16_t opcode_index;
-
- /* Write Enable is handled as atomic prefix */
- if (trans->opcode == SPI_OPCODE_WREN)
- return 0;
-
- read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
- for (opcode_index = 0; opcode_index < cntlr.menubytes;
- opcode_index++) {
- if (opmenu[opcode_index] == trans->opcode)
- break;
- }
+ }
- if (opcode_index == cntlr.menubytes) {
- printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
- trans->opcode);
- return -1;
- }
+ /* The lock is on. See if what we need is on the menu. */
+ uint8_t optype;
+ uint16_t opcode_index;
- optypes = readw_(cntlr.optype);
- optype = (optypes >> (opcode_index * 2)) & 0x3;
- if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
- optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
- trans->bytesout >= 3) {
- /* We guessed wrong earlier. Fix it up. */
- trans->type = optype;
- }
- if (optype != trans->type) {
- printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
- optype);
- return -1;
- }
- return opcode_index;
+ /* Write Enable is handled as atomic prefix */
+ if (trans->opcode == SPI_OPCODE_WREN)
+ return 0;
+
+ read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
+ for (opcode_index = 0; opcode_index < cntlr.menubytes;
+ opcode_index++) {
+ if (opmenu[opcode_index] == trans->opcode)
+ break;
+ }
+
+ if (opcode_index == cntlr.menubytes) {
+ printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
+ trans->opcode);
+ return -1;
+ }
+
+ optypes = readw_(cntlr.optype);
+ optype = (optypes >> (opcode_index * 2)) & 0x3;
+ if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
+ optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
+ trans->bytesout >= 3) {
+ /* We guessed wrong earlier. Fix it up. */
+ trans->type = optype;
+ }
+ if (optype != trans->type) {
+ printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
+ optype);
+ return -1;
}
+ return opcode_index;
}
static int spi_setup_offset(spi_transaction *trans)