diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-29 18:31:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 19:27:53 +0200 |
| commit | 038e7247dc9705ff2d47dd90ec9a807f6feb52ba (patch) | |
| tree | 8cca6a6db31d20a8e045ee5892e8f9cb8de43f8d /src/soc/intel/braswell | |
| parent | f9e7d1b0ca7282a0d51313a68f90e9298c0c46c6 (diff) | |
| download | coreboot-038e7247dc9705ff2d47dd90ec9a807f6feb52ba.tar.xz | |
src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/include/soc/iosf.h | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7fa4b790fd..4dca11019e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -100,7 +100,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE default 0x800 help The amount of anticipated stack usage from the data cache - during pre-ram rom stage execution. + during pre-ram ROM stage execution. config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index 5afca3e123..c0b3f06cc2 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -122,11 +122,11 @@ void reg_script_write_iosf(struct reg_script_context *ctx); /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ #define BUNIT_BMBOUND 0x25 /* - * BMBOUND_HI describes the available ram above 4GiB. It has a + * BMBOUND_HI describes the available RAM above 4GiB. It has a * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB * granularity care needs to be taken with the e820 map to account for a hole - * in the ram. + * in the RAM. */ #define BUNIT_BMBOUND_HI 0x26 #define BUNIT_MMCONF_REG 0x27 |