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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-26 14:03:31 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-08 19:16:24 +0100
commit2bad1e7f491ea9347899498d7d8dde4e1dd9b6d4 (patch)
tree7a1273925b7401e9d4fbe019cda72faea0494de5 /src/soc/intel/braswell
parent76679d1e963824aade23b7b8fec69c6a1eed4a08 (diff)
downloadcoreboot-2bad1e7f491ea9347899498d7d8dde4e1dd9b6d4.tar.xz
intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE
Not referenced in code. Change-Id: Iea91f4418eb122fb647ec0f4f42cb786e8eadf23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/Kconfig13
1 files changed, 3 insertions, 10 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index b587988532..ddd7051ec7 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -75,9 +75,9 @@ config SMM_RESERVED_SIZE
# Cache As RAM region layout:
#
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
-# | Stack |\
-# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE
-# | v |/
+# | Stack |
+# | | |
+# | v |
# +-------------+
# | ^ |
# | | |
@@ -97,13 +97,6 @@ config DCACHE_RAM_SIZE
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
-config DCACHE_RAM_ROMSTAGE_STACK_SIZE
- hex
- default 0x800
- help
- The amount of anticipated stack usage from the data cache
- during pre-ram ROM stage execution.
-
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n