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authorLee Leahy <leroy.p.leahy@intel.com>2017-03-16 17:30:09 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-17 02:35:47 +0100
commit6598b91fe34fe9e6e6fbea592ead5e4fc2900551 (patch)
tree42b70feec4183be3a87249d73565bb1a56c1c5e6 /src/soc/intel/braswell
parentf4c4ab9826b521666d5ba887e69a636428ac9eb2 (diff)
downloadcoreboot-6598b91fe34fe9e6e6fbea592ead5e4fc2900551.tar.xz
soc/intel/braswell: Fix spacing issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxE) ERROR: spaces required around that '=' (ctx:WxV) ERROR: code indent should use tabs where possible WARNING: space prohibited between function name and open parenthesis '(' WARNING: please, no spaces at the start of a line TEST=Build for cyan Change-Id: I84d4204585b498b695608c5008fdfb7961e2416f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18869 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/acpi.c4
-rw-r--r--src/soc/intel/braswell/chip.h12
-rw-r--r--src/soc/intel/braswell/gpio.c6
-rw-r--r--src/soc/intel/braswell/gpio_support.c4
-rw-r--r--src/soc/intel/braswell/include/soc/gpio.h2
5 files changed, 14 insertions, 14 deletions
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 0e866a5857..163d7a9eea 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -498,7 +498,7 @@ unsigned long southcluster_write_acpi_tables(device_t device,
if (ssdt2->length) {
current += ssdt2->length;
acpi_add_table(rsdp, ssdt2);
- printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2,
+ printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2,
ssdt2->length);
current = acpi_align_current(current);
} else {
@@ -517,7 +517,7 @@ void southcluster_inject_dsdt(device_t device)
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 864f214008..fc57a6a95d 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -34,8 +34,8 @@
#define MEM_LPDDR3 1
enum lpe_clk_src {
- LPE_CLK_SRC_XTAL,
- LPE_CLK_SRC_PLL,
+ LPE_CLK_SRC_XTAL,
+ LPE_CLK_SRC_PLL,
};
enum usb_comp_bg_value {
@@ -74,10 +74,10 @@ struct soc_intel_braswell_config {
int pcie_wake_enable;
/* Program USB2_COMPBG register.
- * [10:7] - select vref to AFE port
- * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV,
- * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV
- */
+ * [10:7] - select vref to AFE port
+ * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV,
+ * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV
+ */
enum usb_comp_bg_value usb_comp_bg;
diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c
index b85cde3e73..a742f73119 100644
--- a/src/soc/intel/braswell/gpio.c
+++ b/src/soc/intel/braswell/gpio.c
@@ -59,9 +59,9 @@ static const u8 gpecommunity_gpio_to_pad[GP_EAST_COUNT] = {
/* GPIO Community descriptions */
static const struct gpio_bank gpnorth_community = {
.gpio_count = GP_NORTH_COUNT,
- .gpio_to_pad = gpncommunity_gpio_to_pad ,
- .pad_base = COMMUNITY_GPNORTH_BASE ,
- .has_gpe_en = GPE_CAPABLE ,
+ .gpio_to_pad = gpncommunity_gpio_to_pad,
+ .pad_base = COMMUNITY_GPNORTH_BASE,
+ .has_gpe_en = GPE_CAPABLE,
.has_wake_en = 1,
};
diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c
index 73f829b5f7..5ca34ec3ab 100644
--- a/src/soc/intel/braswell/gpio_support.c
+++ b/src/soc/intel/braswell/gpio_support.c
@@ -103,7 +103,7 @@ static int gpio_get_community_num(gpio_t gpio_num, int *pad)
static void gpio_config_pad(gpio_t gpio_num, const struct soc_gpio_map *cfg)
{
int comm = 0;
- int pad_num =0;
+ int pad_num = 0;
uint32_t *pad_config0_reg;
uint32_t *pad_config1_reg;
int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
@@ -143,7 +143,7 @@ void gpio_input(gpio_t gpio_num)
int gpio_get(gpio_t gpio_num)
{
int comm = 0;
- int pad_num =0;
+ int pad_num = 0;
uint32_t *pad_config0_reg;
u32 pad_value;
int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 3c56f6ae32..4abc9f47bf 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -315,7 +315,7 @@
| PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \
| PAD_INT_SEL(int_sel), \
.pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \
- .int_mask = 1 ,\
+ .int_mask = 1,\
.wake_mask = 1 }
#define GPIO_SMI(int_sel) \