diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2015-09-08 16:12:44 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-17 14:23:40 +0000 |
commit | a1c8b34d7b1b3a8df5b86faab79010c06b037445 (patch) | |
tree | a3ef38b194fe7094ee4ee7e7dd9ab6a440115b06 /src/soc/intel/braswell | |
parent | 47a0b8494b59cf292dcc3372a01ee597b6de3923 (diff) | |
download | coreboot-a1c8b34d7b1b3a8df5b86faab79010c06b037445.tar.xz |
skylake: Use common ACPI _SWS code
Enable and use the common code for filling out the NVS data used
by the _SWS methods. Add a function to provide the wake source
data. With Deep S3 enabled skylake does not retain the contents
of the PM1_EN register so instead just select the wake related
events in PM1_STS.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=tested on glados by checking for valid _SWS string in
/sys/firmware/log after suspend/resume. Wake sources that were
tested are RTC, power button, keypress, trackpad, and wifi.
Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0
Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298169
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11648
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell')
0 files changed, 0 insertions, 0 deletions