intel fsp1_1: prepare for romstage vboot verification split

In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:

- Add fsp/car.h to house the declarations for functions in
  the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
  cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
  in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
  romstage separated from cache-as-ram as well as one that
  is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
  soc/intel/{braswell,common,skylake}.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 2 insertions, 10 deletions

diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 87b1af09df..0b1eab5f04 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -31,10 +31,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#endif
 #include <elog.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
@@ -170,7 +166,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
 }
 
 /* SOC initialization before the console is enabled */
-void soc_pre_console_init(void)
+void car_soc_pre_console_init(void)
 {
 	/* Early chipset initialization */
 	program_base_addresses();
@@ -178,16 +174,12 @@ void soc_pre_console_init(void)
 }
 
 /* SOC initialization after console is enabled */
-void soc_romstage_init(struct romstage_params *params)
+void car_soc_post_console_init(void)
 {
 	/* Continue chipset initialization */
 	set_max_freq();
 	spi_init();
 
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-	/* Ensure the EC is in the right mode for recovery */
-	google_chromeec_early_init();
-#endif
 	lpc_init();
 }