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authorJulius Werner <jwerner@chromium.org>2019-03-05 16:53:33 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-08 08:33:24 +0000
commitcd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch)
tree8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/braswell
parentb3a8cc54dbaf833c590a56f912209a5632b71f49 (diff)
downloadcoreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/acpi.c12
-rw-r--r--src/soc/intel/braswell/acpi/lpc.asl2
-rw-r--r--src/soc/intel/braswell/gfx.c2
-rw-r--r--src/soc/intel/braswell/include/soc/pm.h2
-rw-r--r--src/soc/intel/braswell/memmap.c2
-rw-r--r--src/soc/intel/braswell/northcluster.c2
-rw-r--r--src/soc/intel/braswell/romstage/romstage.c4
-rw-r--r--src/soc/intel/braswell/smihandler.c10
-rw-r--r--src/soc/intel/braswell/spi.c2
9 files changed, 19 insertions, 19 deletions
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 4ace22aab9..dbd29503c7 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -89,15 +89,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
-#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
+#if CONFIG(CONSOLE_CBMEM)
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
#endif
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
@@ -492,12 +492,12 @@ unsigned long southcluster_write_acpi_tables(struct device *device,
acpi_header_t *ssdt2;
global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (!IS_ENABLED(CONFIG_DISABLE_HPET)) {
+ if (!CONFIG(DISABLE_HPET)) {
current = acpi_write_hpet(device, current, rsdp);
current = acpi_align_current(current);
}
- if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) {
+ if (CONFIG(INTEL_GMA_ADD_VBT)) {
igd_opregion_t *opregion;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
@@ -543,7 +543,7 @@ void southcluster_inject_dsdt(struct device *device)
if (gnvs) {
acpi_create_gnvs(gnvs);
/* Fill in the Wifi Region id */
- if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN))
+ if (CONFIG(HAVE_REGULATORY_DOMAIN))
gnvs->cid1 = wifi_regulatory_domain();
else
gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index 067b05f6de..6b2ececc40 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -48,7 +48,7 @@ Device (LPCB)
})
}
-#if !IS_ENABLED(CONFIG_DISABLE_HPET)
+#if !CONFIG(DISABLE_HPET)
Device (HPET)
{
Name (_HID, EISAID("PNP0103"))
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index 023a5b9ee0..16751fbadd 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -67,7 +67,7 @@ static void gfx_init(struct device *dev)
printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
- if (!IS_ENABLED(CONFIG_RUN_FSP_GOP)) {
+ if (!CONFIG(RUN_FSP_GOP)) {
/* Pre VBIOS Init */
gfx_pre_vbios_init(dev);
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 5d8c332feb..5063342955 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -242,7 +242,7 @@ void enable_gpe(uint32_t mask);
void disable_gpe(uint32_t mask);
void disable_all_gpe(void);
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
void southcluster_log_state(void);
#else
static inline void southcluster_log_state(void) {}
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index d2653f3093..207c843d52 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -37,7 +37,7 @@ void smm_region(void **start, size_t *size)
size_t mmap_region_granularity(void)
{
/* Align to TSEG size when SMM is in use, and 8MiB by default */
- return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? smm_region_size()
+ return CONFIG(HAVE_SMI_HANDLER) ? smm_region_size()
: 8 << 20;
}
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index c54c2c8f3c..9267448697 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -165,7 +165,7 @@ static void nc_read_resources(struct device *dev)
size_k = RES_IN_KIB(0x00100000);
mmio_resource(dev, index++, base_k, size_k);
- if (IS_ENABLED(CONFIG_CHROMEOS))
+ if (CONFIG(CHROMEOS))
chromeos_reserve_ram_oops(dev, index++);
}
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 5fe3550509..e4180641a6 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -161,7 +161,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
if (ps->pm1_sts & WAK_STS) {
switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
case ACPI_S3:
- if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+ if (CONFIG(HAVE_ACPI_RESUME))
prev_sleep_state = ACPI_S3;
break;
case ACPI_S5:
@@ -229,7 +229,7 @@ void soc_memory_init_params(struct romstage_params *params,
config = dev->chip_info;
printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
- upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
+ upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ?
config->PcdMrcInitTsegSize : 0;
upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1;
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index 1f02269cec..a72330915e 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -153,7 +153,7 @@ static void southbridge_smi_sleep(void)
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -259,7 +259,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
return NULL;
}
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -292,7 +292,7 @@ static void finalize(void)
}
finalize_done = 1;
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
@@ -345,7 +345,7 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
case APM_CNT_ELOG_GSMI:
southbridge_smi_gsmi();
break;
@@ -368,7 +368,7 @@ static void southbridge_smi_pm1(void)
*/
if (pm1_sts & PWRBTN_STS) {
/* power button pressed */
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
disable_pm1_control(-1UL);
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index fa22cf7c06..c87232dd92 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -119,7 +119,7 @@ enum {
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
};
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+#if CONFIG(DEBUG_SPI_FLASH)
static u8 readb_(void *addr)
{