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| author | Aaron Durbin <adurbin@chromium.org> | 2016-05-05 10:38:03 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-05-06 16:50:00 +0200 |
| commit | f5ff854c3678e8fe140dcc5c2f4595ee70ddfe4f (patch) | |
| tree | 938a1d9ccbf10d796772c237dc4380a0ce6ebd75 /src/soc/intel/braswell | |
| parent | ef1052918775d321928410aebedeb21ac96b36c0 (diff) | |
| download | coreboot-f5ff854c3678e8fe140dcc5c2f4595ee70ddfe4f.tar.xz | |
soc/intel: indicate to build system that XIP_ROM_SIZE isn't used
The XIP_ROM_SIZE Kconfig variable isn't used for these chipsets.
Therefore, indicate as such so that romstage can be placed in
cbfs less rigidly.
Change-Id: If5cae10b90e05029df56c282e8adf37fa0102955
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14626
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 3c6f7884de..3466aade67 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select PARALLEL_MP select PCIEXP_ASPM |