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| author | Aaron Durbin <adurbin@chromium.org> | 2016-03-07 16:23:47 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-03-08 23:58:01 +0100 |
| commit | 2a08137feebaf0f8f55feeff00096f5a9d03f44c (patch) | |
| tree | 269676f6d212e7d02d4069891d629881ccb7b034 /src/soc/intel/braswell | |
| parent | f5452085979d9031023b1b810abf0493757e6287 (diff) | |
| download | coreboot-2a08137feebaf0f8f55feeff00096f5a9d03f44c.tar.xz | |
x86 chipsets: utilize x86_setup_mtrrs_with_detect()
For all the chipsets which were performing the following sequence:
x86_setup_fixed_mtrrs();
x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
Replace that with x86_setup_mtrrs_with_detect() since it is equivalent.
Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13936
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/cpu.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index feb9d9b84a..71af487840 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -89,8 +89,7 @@ void soc_init_cpus(device_t dev) __FILE__, __func__, dev_name(dev)); /* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, |