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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-06 12:07:05 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-11-08 07:51:18 +0000
commit056fbe49ff9cccc7646371452431a05b47544057 (patch)
tree4bc2ea46dae5de31731678ba2eb86fa698034a3c /src/soc/intel/braswell
parentc86fc8e63d81251a5da80ed55e4fbc9900a900d9 (diff)
downloadcoreboot-056fbe49ff9cccc7646371452431a05b47544057.tar.xz
ELOG, soc/intel: Avoid some preprocessor use
Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/include/soc/pm.h4
-rw-r--r--src/soc/intel/braswell/smm.c3
2 files changed, 2 insertions, 5 deletions
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 5063342955..744fcf085f 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -242,11 +242,7 @@ void enable_gpe(uint32_t mask);
void disable_gpe(uint32_t mask);
void disable_all_gpe(void);
-#if CONFIG(ELOG)
void southcluster_log_state(void);
-#else
-static inline void southcluster_log_state(void) {}
-#endif
/* Return non-zero when RTC failure happened. */
int rtc_failure(void);
diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c
index 364cda5b5a..c108a3629e 100644
--- a/src/soc/intel/braswell/smm.c
+++ b/src/soc/intel/braswell/smm.c
@@ -39,7 +39,8 @@ void smm_southbridge_clear_state(void)
uint32_t smi_en;
/* Log events from chipset before clearing */
- southcluster_log_state();
+ if (CONFIG(ELOG))
+ southcluster_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());