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authorElyes HAOUAS <ehaouas@noos.fr>2019-11-30 19:38:23 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-19 05:41:08 +0000
commit608fbf81109902cfd1775e61b18a2c37e2084d9d (patch)
tree5357fe9849863a0a3ec5f94387e61e25b3f7a185 /src/soc/intel/braswell
parentd51ee90f122de103756a26842f17ded2465db1a3 (diff)
downloadcoreboot-608fbf81109902cfd1775e61b18a2c37e2084d9d.tar.xz
src/soc/intel: Remove unused <stdlib.h>
Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33686 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/cpu.c1
-rw-r--r--src/soc/intel/braswell/ramstage.c1
-rw-r--r--src/soc/intel/braswell/smihandler.c1
3 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index a44b9cb2e5..4288394808 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -33,7 +33,6 @@
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <soc/ramstage.h>
-#include <stdlib.h>
/* Core level MSRs */
static const struct reg_script core_msr_script[] = {
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index d6a1cda8b3..f8011fdb73 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -37,7 +37,6 @@
#include <soc/ramstage.h>
#include <soc/intel/common/acpi.h>
#include <boardid.h>
-#include <stdlib.h>
#include <string.h>
#define SHOW_PATTRS 1
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index d0306caaa3..80b142aad8 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -29,7 +29,6 @@
#include <soc/pm.h>
#include <spi-generic.h>
#include <stdint.h>
-#include <stdlib.h>
#include <soc/gpio.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */