diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-03-21 15:38:06 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-26 16:49:13 +0000 |
| commit | c3385070d6e86dbde71dddbdef94ffa5579f9d11 (patch) | |
| tree | e2d65c2c0550b67092d008ca31c3c22e11b932f0 /src/soc/intel/braswell | |
| parent | 9df72e0471296d9bc2981646490c1f8b5b1e54e0 (diff) | |
| download | coreboot-c3385070d6e86dbde71dddbdef94ffa5579f9d11.tar.xz | |
soc/{amd,intel}/chip: Use local include for chip.h
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/braswell/include/soc/ramstage.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 3 |
3 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 7617d53644..4be13cdea3 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -23,6 +22,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + static void pci_domain_set_resources(struct device *dev) { printk(BIOS_SPEW, "%s/%s (%s)\n", diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index d735de5885..f197bc8e1f 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -17,10 +17,11 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <chip.h> #include <device/device.h> #include <fsp/ramstage.h> +#include "../../chip.h" + #define V_PCH_LPC_RID_A0 0x00 // A0 Stepping #define V_PCH_LPC_RID_A1 0x04 // A1 Stepping #define V_PCH_LPC_RID_A2 0x08 // A2 Stepping diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index ae2eac8e20..342b05cf50 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -22,7 +22,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/cbfs.h> -#include <chip.h> #include <cpu/x86/mtrr.h> #include <console/console.h> #include <device/device.h> @@ -44,6 +43,8 @@ #include <build.h> #include <pc80/mc146818rtc.h> +#include "../chip.h" + void program_base_addresses(void) { uint32_t reg; |