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authorAaron Durbin <adurbin@chromium.org>2015-09-30 09:12:57 -0500
committerAaron Durbin <adurbin@gmail.com>2015-10-11 23:55:41 +0000
commitcc5ac17fab97bd16f3122bb492fbdc28644c8567 (patch)
tree3c1b0a9c0d8155b06e0556567905d52d9562a800 /src/soc/intel/braswell
parent3c4053fa59a8654b2f10cf175915914c37da9daf (diff)
downloadcoreboot-cc5ac17fab97bd16f3122bb492fbdc28644c8567.tar.xz
soc/intel/common: remove chipset specific calls
The report_platform_info() and set_max_freq() are not being used similarly on skylake and braswell. With the addition of other SoCs I suspect a similar pattern will emerge. Instead of having weak functions to ensure things link with the hardcoded policy push these calls into their respective SoC homes. For parity, both skylake and braswell were updated to be consistent with the same calls prior to this patch. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Built braswell. Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/303334 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11815 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/include/soc/romstage.h1
-rw-r--r--src/soc/intel/braswell/romstage/romstage.c1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index a735c04db5..0f24f71c9f 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -33,6 +33,7 @@ void tco_disable(void);
void punit_init(void);
int early_spi_read_wpsr(u8 *sr);
void mainboard_fill_spd_data(struct pei_data *pei_data);
+void set_max_freq(void);
/* romstage_common.c functions */
void program_base_addresses(void);
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 00710fe837..87b1af09df 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -181,6 +181,7 @@ void soc_pre_console_init(void)
void soc_romstage_init(struct romstage_params *params)
{
/* Continue chipset initialization */
+ set_max_freq();
spi_init();
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)