soc/intel: Rename some SMM support functions

Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.

Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 15 insertions, 17 deletions

diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 1b1548ad6d..72b1d8ee89 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -18,7 +18,9 @@
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/common/common.h>
+#include <cpu/intel/em64t100_save_state.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>
@@ -26,7 +28,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
 #include <reg_script.h>
 #include <soc/iosf.h>
 #include <soc/msr.h>
@@ -217,10 +218,10 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.get_microcode_info = get_microcode_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = relocation_handler,
-	.post_mp_init = southcluster_smm_enable_smi,
+	.post_mp_init = smm_southbridge_enable_smi,
 };
 
 void soc_init_cpus(struct device *dev)
diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c
index 77547b8a8e..14f95e1867 100644
--- a/src/soc/intel/braswell/gpio.c
+++ b/src/soc/intel/braswell/gpio.c
@@ -176,7 +176,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
 	route_reg, alt_gpio_smi, gpe0a_en);
 #endif
 	/* Save as an smm param */
-	southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
+	smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
 }
 
 
diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h
index 93065a2a94..68b4cb0025 100644
--- a/src/soc/intel/braswell/include/soc/smm.h
+++ b/src/soc/intel/braswell/include/soc/smm.h
@@ -17,13 +17,7 @@
 #ifndef _SOC_SMM_H_
 #define _SOC_SMM_H_
 
-
-#if ENV_RAMSTAGE
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_param(int param, uint32_t data);
-#endif
+#include <types.h>
 
 enum {
 	SMM_SAVE_PARAM_GPIO_ROUTE = 0,
@@ -31,4 +25,6 @@ enum {
 	SMM_SAVE_PARAM_COUNT
 };
 
+void smm_southcluster_save_param(int param, uint32_t data);
+
 #endif /* _SOC_SMM_H_ */
diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c
index dc779bbb80..4ae7f3f236 100644
--- a/src/soc/intel/braswell/pcie.c
+++ b/src/soc/intel/braswell/pcie.c
@@ -148,7 +148,7 @@ static void pcie_enable(struct device *dev)
 		strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
 
 		if (config->pcie_wake_enable)
-			southcluster_smm_save_param(
+			smm_southcluster_save_param(
 				SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
 	}
 
diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c
index fe681c9d90..364cda5b5a 100644
--- a/src/soc/intel/braswell/smm.c
+++ b/src/soc/intel/braswell/smm.c
@@ -19,6 +19,7 @@
 #include <device/mmio.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <soc/iomap.h>
@@ -28,12 +29,12 @@
 /* Save settings which will be committed in SMI functions. */
 static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
 
-void southcluster_smm_save_param(int param, uint32_t data)
+void smm_southcluster_save_param(int param, uint32_t data)
 {
 	smm_save_params[param] = data;
 }
 
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	uint32_t smi_en;
 
@@ -58,7 +59,7 @@ void southcluster_smm_clear_state(void)
 	clear_pmc_status();
 }
 
-static void southcluster_smm_route_gpios(void)
+static void smm_southcluster_route_gpios(void)
 {
 	void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT);
 	const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
@@ -82,7 +83,7 @@ static void southcluster_smm_route_gpios(void)
 	outl(alt_gpio_reg, alt_gpio_smi);
 }
 
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
 	uint16_t pm1_events = PWRBTN_EN | GBL_EN;
 
@@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void)
 	disable_gpe(PME_B0_EN);
 
 	/* Set up the GPIO route. */
-	southcluster_smm_route_gpios();
+	smm_southcluster_route_gpios();
 
 	/*
 	 * Enable SMI generation: