summaryrefslogtreecommitdiff
path: root/src/soc/intel/braswell
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-07-20 23:31:59 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-07-24 18:34:37 +0000
commite750b38e4834867ec362b59f150ef6ae9fe888c6 (patch)
treefa85e7241ca2496c45e103a2a2c62ce053b473cc /src/soc/intel/braswell
parent6b27c38f4afdd7b20100c4a772fa4077ae437cf1 (diff)
downloadcoreboot-e750b38e4834867ec362b59f150ef6ae9fe888c6.tar.xz
cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/cpu.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 31b1b78142..85b04ac81f 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -195,10 +195,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_BASE, smrr);
+ wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_MASK, smrr);
+ wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase;