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| author | Nico Huber <nico.h@gmx.de> | 2019-10-12 15:16:33 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-16 11:11:42 +0000 |
| commit | ad91b18c6418d2ed862e54cc26019172561200af (patch) | |
| tree | 4d301d942c23d88373640e0df04e9ee9a379374d /src/soc/intel/braswell | |
| parent | 5e8afce88f3bd4914be0b472559486c59fe58f41 (diff) | |
| download | coreboot-ad91b18c6418d2ed862e54cc26019172561200af.tar.xz | |
intel/skylake: Use new PCIe RP devicetree update
The old code stumbled when the whole first group of root ports
was disabled and also made the (sometimes wrong) assumption
that FSP would only hide function 0 if we explicitly told it
to disable it.
Change-Id: Ia6938ca6929c6d9d0293c4f0f0421e38bf53fb55
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36702
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell')
0 files changed, 0 insertions, 0 deletions