diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2017-09-26 19:34:35 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-30 07:19:52 +0000 |
| commit | c7edf18f7c763762676eeb3bad084cd4c032cfcf (patch) | |
| tree | 08e309b6b6c3c45d87b3d86b4e5a0b8d2d311875 /src/soc/intel/braswell | |
| parent | 0bcd86a14af2ee876e22cc2bcd7b1d4dee505cd3 (diff) | |
| download | coreboot-c7edf18f7c763762676eeb3bad084cd4c032cfcf.tar.xz | |
soc/intel/common/opregion: Get rid of opregion.c
Get rid of custom opregion implementation and use drivers/intel/gma/opregion
implementation instead.
Test: boot Windows 10 on google/chell and google/edgar using Tianocore
payload with GOP init, observe Intel graphics driver loaded and functional.
Change-Id: I5f78e9030df12da5369d142dda5c59e576ebcef7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21703
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/braswell/acpi.c | 39 | ||||
| -rw-r--r-- | src/soc/intel/braswell/include/soc/gfx.h | 3 |
3 files changed, 5 insertions, 40 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index dc2f40de1d..1154c041d1 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -48,7 +48,8 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP select GENERIC_GPIO_LIB - select SOC_INTEL_COMMON_GFX_OPREGION + select INTEL_GMA_ACPI + select INTEL_GMA_SWSMISCI config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 61ae20354c..61ad03d388 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -31,7 +31,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <ec/google/chromeec/ec.h> -#include <soc/intel/common/opregion.h> +#include <drivers/intel/gma/opregion.h> #include <rules.h> #include <soc/acpi.h> #include <soc/gfx.h> @@ -476,40 +476,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) /* Initialize IGD OpRegion, called from ACPI code */ static int update_igd_opregion(igd_opregion_t *opregion) { - u16 reg16; - struct device *igd; - - /* TODO Initialize Mailbox 1 */ - opregion->mailbox1.clid = 1; - - /* TODO Initialize Mailbox 3 */ - opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; - opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; - opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ - opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; - opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; - opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; - opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; - opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; - opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; - opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; - opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; - opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; - opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; - opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; - opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; - - /* - * TODO This needs to happen in S3 resume, too. - * Maybe it should move to the finalize handler - */ - igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); - - pci_write_config32(igd, ASLS, (u32)opregion); - reg16 = pci_read_config16(igd, SWSCI); - reg16 &= ~(1 << 0); - reg16 |= (1 << 15); - pci_write_config16(igd, SWSCI, reg16); + /* FIXME: Add platform specific mailbox initialization */ return 0; } @@ -528,7 +495,7 @@ unsigned long southcluster_write_acpi_tables(device_t device, printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); opregion = (igd_opregion_t *)current; - init_igd_opregion(opregion); + intel_gma_init_igd_opregion(opregion); update_igd_opregion(opregion); current += sizeof(igd_opregion_t); current = acpi_align_current(current); diff --git a/src/soc/intel/braswell/include/soc/gfx.h b/src/soc/intel/braswell/include/soc/gfx.h index 5a51620333..c6b802fc42 100644 --- a/src/soc/intel/braswell/include/soc/gfx.h +++ b/src/soc/intel/braswell/include/soc/gfx.h @@ -63,9 +63,6 @@ #define APERTURE_SIZE_256MB (1 << 1) #define APERTURE_SIZE_512MB (3 << 1) -#define SWSCI 0xe8 /* SWSCI enable */ -#define ASLS 0xfc /* OpRegion Base */ - /* Panel control registers */ #define HOTPLUG_CTRL 0x61110 #define PP_CONTROL 0x61204 |