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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-18 19:40:48 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-19 19:31:08 +0000
commit4f14cd8a39e65811af08296633842289efa42927 (patch)
tree1cece9915f897af008d2d83701088b3054c4ab93 /src/soc/intel/broadwell/Kconfig
parent6766f4fd046604e6376c9769cd5f8357dec6a80a (diff)
downloadcoreboot-4f14cd8a39e65811af08296633842289efa42927.tar.xz
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/Kconfig')
-rw-r--r--src/soc/intel/broadwell/Kconfig10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 21c9b6f12a..f01777f4f0 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -166,16 +166,6 @@ config PRE_GRAPHICS_DELAY
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- help
- The romstage code caches the loaded ramstage program in SMM space.
- On S3 wake the romstage will copy over a fresh ramstage that was
- cached in the SMM space. This option determines the action to take
- when the ramstage cache is invalid. If selected the system will
- reset otherwise the ramstage will be reloaded from cbfs.
-
config INTEL_PCH_UART_CONSOLE
bool "Use Serial IO UART for console"
default n