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authorArthur Heymans <arthur@aheymans.xyz>2018-12-22 16:02:25 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-15 17:56:56 +0000
commit5bb15f1a4d18bafaf51b17fd9ea6d861f2b9ebd2 (patch)
tree8bedf540cdcf995931cb65799c881ad9a697cf26 /src/soc/intel/broadwell/Kconfig
parent56f768774a25320d738febf99c335abdb6eeafbe (diff)
downloadcoreboot-5bb15f1a4d18bafaf51b17fd9ea6d861f2b9ebd2.tar.xz
soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected. Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/broadwell/Kconfig')
-rw-r--r--src/soc/intel/broadwell/Kconfig21
1 files changed, 9 insertions, 12 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 83ccf7b9d8..9dd2f4f414 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -44,6 +44,8 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select NO_FIXED_XIP_ROM_SIZE
+ select C_ENVIRONMENT_BOOTBLOCK
+ select NO_BOOTBLOCK_CONSOLE
config PCIEXP_ASPM
bool
@@ -69,18 +71,6 @@ config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE
-config BOOTBLOCK_CPU_INIT
- string
- default "soc/intel/broadwell/bootblock/cpu.c"
-
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "soc/intel/broadwell/bootblock/systemagent.c"
-
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "soc/intel/broadwell/bootblock/pch.c"
-
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
@@ -123,6 +113,13 @@ config DCACHE_RAM_MRC_VAR_SIZE
help
The amount of cache-as-ram region required by the reference code.
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
+
config HAVE_MRC
bool "Add a Memory Reference Code binary"
help