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| author | Patrick Rudolph <siro@das-labor.org> | 2018-10-01 19:17:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:35:25 +0000 |
| commit | 45022ae056cdbf58429b77daf2da176306312801 (patch) | |
| tree | 4218666e3c14e41232778c4ceff301292b3c61d9 /src/soc/intel/broadwell/Makefile.inc | |
| parent | 33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff) | |
| download | coreboot-45022ae056cdbf58429b77daf2da176306312801.tar.xz | |
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/Makefile.inc')
| -rw-r--r-- | src/soc/intel/broadwell/Makefile.inc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index c4f45388f8..4e4d3ebe55 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -43,8 +43,6 @@ romstage-y += pmutil.c smm-y += pmutil.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += reset.c -romstage-y += reset.c ramstage-y += sata.c ramstage-y += serialio.c ramstage-y += smbus.c |