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| author | Iru Cai <mytbk920423@gmail.com> | 2020-11-02 13:13:32 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2021-05-21 20:30:32 +0800 |
| commit | d0683acb0ce411f13fc1a21fb911422de3e903bf (patch) | |
| tree | f591219040b4bdefd4b0767efad0f230183abe91 /src/soc/intel/broadwell/Makefile.inc | |
| parent | 35fd3331f471144d40358a85a43529fa5f172075 (diff) | |
| download | coreboot-d0683acb0ce411f13fc1a21fb911422de3e903bf.tar.xz | |
add broadwell_refcode.asm
Diffstat (limited to 'src/soc/intel/broadwell/Makefile.inc')
| -rw-r--r-- | src/soc/intel/broadwell/Makefile.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 55eddf18fd..971a5dc939 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) subdirs-y += pch +subdirs-y += refcode bootblock-y += bootblock.c @@ -19,7 +20,7 @@ ramstage-y += minihd.c ramstage-y += northbridge.c ramstage-y += pei_data.c romstage-y += pei_data.c -ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c +ramstage-y += refcode.c CPPFLAGS_common += -Isrc/soc/intel/broadwell/include |