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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-11-29 13:36:54 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-05 13:32:42 +0000 |
commit | 90cca5422d2d44ee96cbcd420a878b2fb1b3e111 (patch) | |
tree | 8d5f2e8c8b54ae2a0c69a8eb2e673d4feb03efe9 /src/soc/intel/broadwell/Makefile.inc | |
parent | 9fca297ca44eb388229523f820f57f795b49af15 (diff) | |
download | coreboot-90cca5422d2d44ee96cbcd420a878b2fb1b3e111.tar.xz |
soc/intel/broadwell: Implement postcar stage
This does the following:
- Reuse the cpu/intel/car/non-evict CAR setup and exit.
- Use postcar_frame functions to set up the postcar frame
Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/Makefile.inc')
-rw-r--r-- | src/soc/intel/broadwell/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 4e4d3ebe55..caf963c8e0 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += me_status.c romstage-y += me_status.c ramstage-y += memmap.c romstage-y += memmap.c +postcar-y += memmap.c ramstage-y += minihd.c ramstage-y += monotonic_timer.c smm-y += monotonic_timer.c @@ -55,6 +56,7 @@ ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-y += stage_cache.c romstage-y += stage_cache.c +postcar-y += stage_cache.c ramstage-y += systemagent.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c @@ -65,6 +67,8 @@ ramstage-y += ehci.c ramstage-y += xhci.c smm-y += xhci.c +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S + ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin |