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| author | Duncan Laurie <dlaurie@chromium.org> | 2014-05-05 12:42:35 -0500 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-10-22 03:47:10 +0200 |
| commit | 61680274c1ded5ea095b15b689f83d5d670d2aae (patch) | |
| tree | 319efef1d3ab9c41b7fca274cd80827f0d8136f1 /src/soc/intel/broadwell/acpi/device_nvs.asl | |
| parent | e256295218266325a77e8b6a207e71bedd9a9359 (diff) | |
| download | coreboot-61680274c1ded5ea095b15b689f83d5d670d2aae.tar.xz | |
broadwell: ACPI, romstage, and other updates
broadwell: Add romstage usbdebug support
Reviewed-on: https://chromium-review.googlesource.com/199412
(cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)
broadwell: Add romstage code to configure PCH UART for console
Reviewed-on: https://chromium-review.googlesource.com/199807
(cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)
broadwell: Expand the PCI device convenience macros
Reviewed-on: https://chromium-review.googlesource.com/199891
(cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)
broadwell: Add ramstage driver for ADSP
Reviewed-on: https://chromium-review.googlesource.com/199892
(cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)
broadwell: Update ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/201080
(cherry picked from commit 2446b35578eb36e0009415bec340059135751549)
broadwell: Reserve DPR region
Reviewed-on: https://chromium-review.googlesource.com/201081
(cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)
broadwell: Remove old pei_data and add cpu function for romstage
Reviewed-on: https://chromium-review.googlesource.com/201690
(cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)
broadwell: Fixes for graphics without executing VBIOS
Reviewed-on: https://chromium-review.googlesource.com/202356
(cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)
broadwell: Fix compilation failure when loglevel is lowered
Reviewed-on: https://chromium-review.googlesource.com/202357
(cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)
broadwell: Disable GPIO controller interrupt
Reviewed-on: https://chromium-review.googlesource.com/203645
(cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)
broadwell: Add support for E0 stepping
Reviewed-on: https://chromium-review.googlesource.com/205160
(cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)
broadwell: misc updates for CPU driver
Reviewed-on: https://chromium-review.googlesource.com/205161
(cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)
broadwell: Read power state earlier and store in romstage params
Reviewed-on: https://chromium-review.googlesource.com/208151
(cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)
broadwell: Add parameters to pei_data structure
Reviewed-on: https://chromium-review.googlesource.com/208153
(cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)
broadwell: Move platform report output after power state is read
Reviewed-on: https://chromium-review.googlesource.com/208213
(cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)
Squashed 15 commits for broadwell support.
Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6982
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/broadwell/acpi/device_nvs.asl')
| -rw-r--r-- | src/soc/intel/broadwell/acpi/device_nvs.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl index d5af2e8cc9..1d2aa78edb 100644 --- a/src/soc/intel/broadwell/acpi/device_nvs.asl +++ b/src/soc/intel/broadwell/acpi/device_nvs.asl @@ -27,6 +27,7 @@ S4EN, 8, // SPI1 Enable S5EN, 8, // UART0 Enable S6EN, 8, // UART1 Enable S7EN, 8, // SDIO Enable +S8EN, 8, // ADSP Enable /* BAR 0 */ @@ -38,6 +39,7 @@ S4B0, 32, // SPI1 BAR0 S5B0, 32, // UART0 BAR0 S6B0, 32, // UART1 BAR0 S7B0, 32, // SDIO BAR0 +S8B0, 32, // ADSP BAR0 /* BAR 1 */ @@ -49,3 +51,4 @@ S4B1, 32, // SPI1 BAR1 S5B1, 32, // UART0 BAR1 S6B1, 32, // UART1 BAR1 S7B1, 32, // SDIO BAR1 +S8B1, 32, // ADSP BAR1 |