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authorArthur Heymans <arthur@aheymans.xyz>2018-11-28 12:22:59 +0100
committerDuncan Laurie <dlaurie@chromium.org>2018-11-30 21:52:51 +0000
commitf7d1c8d1eb651dcf1c692e33fd662500e93ad1fc (patch)
tree921a33bb7d2bcc3fd663029f91bbbe30ee02111f /src/soc/intel/broadwell/acpi
parent1a9efe3b28b42de4ff8191098cec524de563f02d (diff)
downloadcoreboot-f7d1c8d1eb651dcf1c692e33fd662500e93ad1fc.tar.xz
soc/intel/broadwell: Rework acpi/cpu.asl
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/acpi')
-rw-r--r--src/soc/intel/broadwell/acpi/cpu.asl99
1 files changed, 8 insertions, 91 deletions
diff --git a/src/soc/intel/broadwell/acpi/cpu.asl b/src/soc/intel/broadwell/acpi/cpu.asl
index a202cebc0e..d42d1bbe51 100644
--- a/src/soc/intel/broadwell/acpi/cpu.asl
+++ b/src/soc/intel/broadwell/acpi/cpu.asl
@@ -13,106 +13,23 @@
* GNU General Public License for more details.
*/
-/* These devices are created at runtime */
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-External (\_PR.CP02, DeviceObj)
-External (\_PR.CP03, DeviceObj)
-External (\_PR.CP04, DeviceObj)
-External (\_PR.CP05, DeviceObj)
-External (\_PR.CP06, DeviceObj)
-External (\_PR.CP07, DeviceObj)
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
-/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+/* Notify OS to re-read CPU tables */
Method (PNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x81) // _CST
- Notify (\_PR.CP01, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x81) // _CST
- Notify (\_PR.CP03, 0x81) // _CST
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x81) // _CST
- Notify (\_PR.CP05, 0x81) // _CST
- Notify (\_PR.CP06, 0x81) // _CST
- Notify (\_PR.CP07, 0x81) // _CST
- }
+ \_PR.CNOT (0x81)
}
-/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x80) // _PPC
- Notify (\_PR.CP01, 0x80) // _PPC
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x80) // _PPC
- Notify (\_PR.CP03, 0x80) // _PPC
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x80) // _PPC
- Notify (\_PR.CP05, 0x80) // _PPC
- Notify (\_PR.CP06, 0x80) // _PPC
- Notify (\_PR.CP07, 0x80) // _PPC
- }
+ \_PR.CNOT (0x80)
}
-/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
- If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x82) // _TPC
- Notify (\_PR.CP01, 0x82) // _TPC
- }
- If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x82) // _TPC
- Notify (\_PR.CP03, 0x82) // _TPC
- }
- If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CP04, 0x82) // _TPC
- Notify (\_PR.CP05, 0x82) // _TPC
- Notify (\_PR.CP06, 0x82) // _TPC
- Notify (\_PR.CP07, 0x82) // _TPC
- }
-}
-
-/* Return a package containing enabled processor entries */
-Method (PPKG)
-{
- If (LGreaterEqual (\PCNT, 8)) {
- Return (Package()
- {
- \_PR.CP00,
- \_PR.CP01,
- \_PR.CP02,
- \_PR.CP03,
- \_PR.CP04,
- \_PR.CP05,
- \_PR.CP06,
- \_PR.CP07
- })
- } ElseIf (LGreaterEqual (\PCNT, 4)) {
- Return (Package ()
- {
- \_PR.CP00,
- \_PR.CP01,
- \_PR.CP02,
- \_PR.CP03
- })
- } ElseIf (LGreaterEqual (\PCNT, 2)) {
- Return (Package ()
- {
- \_PR.CP00,
- \_PR.CP01
- })
- } Else {
- Return (Package ()
- {
- \_PR.CP00
- })
- }
+ \_PR.CNOT (0x82)
}