soc/intel/broadwell: Flatten northbridge folder structure

Having folders for bootblock and romstage is no longer necessary.

Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46795
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c
new file mode 100644
index 0000000000..5edfaeecaf
--- /dev/null
+++ b/src/soc/intel/broadwell/bootblock.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/bootblock.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
+
+void bootblock_early_northbridge_init(void)
+{
+	uint32_t reg;
+
+	/*
+	 * The "io" variant of the config access is explicitly used to
+	 * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
+	 * to true. That way all subsequent non-explicit config accesses use
+	 * MCFG. This code also assumes that bootblock_northbridge_init() is
+	 * the first thing called in the non-asm boot block code. The final
+	 * assumption is that no assembly code is using the
+	 * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+	 *
+	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
+	 * 4GiB.
+	 */
+	reg = 0;
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
+	reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
+}