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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-01 22:08:18 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-07 12:59:28 +0100
commit6f66f414a0907f79abf492cd9eca839c0849c7f6 (patch)
tree3e74145128261014798af58111db31d616fd43dd /src/soc/intel/broadwell/bootblock
parent891b6c4d199418a08ba88e42d6c8945ce05205f1 (diff)
downloadcoreboot-6f66f414a0907f79abf492cd9eca839c0849c7f6.tar.xz
PCI ops: MMCONF_SUPPORT_DEFAULT is required
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/bootblock')
-rw-r--r--src/soc/intel/broadwell/bootblock/systemagent.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c
index 7511549efa..1a09f8e49f 100644
--- a/src/soc/intel/broadwell/bootblock/systemagent.c
+++ b/src/soc/intel/broadwell/bootblock/systemagent.c
@@ -23,12 +23,12 @@ static void bootblock_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.