summaryrefslogtreecommitdiff
path: root/src/soc/intel/broadwell/chip.c
diff options
context:
space:
mode:
authorJulius Werner <jwerner@chromium.org>2014-10-20 13:46:39 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-07 18:23:23 +0200
commit4ee4bd5bb000b5c78e3d4a3f0113fe1e46e44851 (patch)
treeb784e37198840e63eb5dacc5aa5611543d06b5d0 /src/soc/intel/broadwell/chip.c
parent18ea2d3fbdf89f60a74dc8aabfdb2aa4d3475754 (diff)
downloadcoreboot-4ee4bd5bb000b5c78e3d4a3f0113fe1e46e44851.tar.xz
broadwell: Change all SoC headers to <soc/headername.h> system
This patch aligns broadwell to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Auron and Samus. Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224507 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/chip.c')
-rw-r--r--src/soc/intel/broadwell/chip.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index eecb0cf1ea..00261522ce 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -20,9 +20,9 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <chip.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/intel/broadwell/chip.h>
static void pci_domain_set_resources(device_t dev)
{